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TPS51200-Q1 Timing diagram

Other Parts Discussed in Thread: TPS51200-Q1, TPS51200

Hi

My customer has question about TPS51200-Q1.
Could you tell me about question?

[Question]
 My customer has question about timing diagram.
 TPS51200-Q1 VIN, VLDO, and EN is conneted to same power lane 3.3V.
 So these is wakeup at same time after VREFIN is high and shutdown at same time before VREFIN is low.
 Is there any problem?

Please show attached file.

4846.TPS51200Q1_Timing diagram.pptx

Best regards,

tateo

  • Hello Tateo,

    The appropriate Applications Engineer has been assigned to answer your question(s). You can expect a follow-up response within a few days.

  • Hi Tateo-san,

    We suggest customer follow the typical timing sequence in datasheet Page 11.
    There is no problem to tie EN to VIN, but we do not recommend to use VLDOIN tied to VIN, as something unexpected like spike would occur.
    Because when Vin=0V, the control circuits are not powered up, so they can not control the LDO output stage which is biased by VLDOIN. Depending on some internal leakage paths, the output stage may or may not turn on when Vin=0 and VLDOIN is powered up. Even simulations can not tell us much because device leakage currents are not well modeled.

    Best regards,
    Jason Liu
  • Thank you for your reply.
    My customer is thinking to change the power sequencing. So my customer has more question.

    - What is recommended time between Vin and EN being valid, and VLDOIN starting ramp?

    Please show attached file.

    Best regards,

    tateo

    TPS51200Q1_Timing diagram_rev2.pptx

  • Hi tateo,

    May I know customer's application, different application have different  timing sequence (Datasheet Page 11).

    Usually VLDOIN could start ramp once VIN and EN are stable. And we suggest REFIN also start ramp after VIN and EN are stable.

    Thanks and best regard,

     Jason Liu

  • Thank you for your reply.

    Application is Car-Infotainment system. I attach a circuit in attached file. Vin, VLDOIN and EN is connected to same power lane 3.3V. My customer is thinking that VLDOIN input to be delay. So my customer need information that recommended time between Vin and EN being valid, and VLDOIN starting ramp. Please show attached file.

    And I appreciate your answer about REFIN. I'll explain to my customer.

    Best Regards,

    tateo

    TPS51200Q1_Timing diagram_rev3.pptx

  • Hi Tateo,
    I understand your idea but have one question, how to implement delay on a power input?
    If using a timer to control something like switch, how to set the start point of this timer?
    And that would cost much, and take much room in PCB boards.
    Why customers cannot use a different power lane for VLDOIN?

    Thanks and best regards,

    Jason Liu

  • Hi Tateo,

    There is no specific timing requirement, as long as VLDOIN is coming up later than VIN and EN, it should be OK. You could tell customer set it something like 10uS.

    One problem is why customer want to use 3.3V as VLDOIN instead of 1.5V. 3.3V input will give much more power loss.

    Best regards,

    Jason Liu

  • I appreciate your kind support. I had meeting with my customer. I suggest sequecing and using power lain. My customer will be re-thinking. I'll contact you if my customer require further consultation.
    Best regards,tateo
  • I appreciate for your kind support. So my customer has one more question.

    My customer designed TPS51200-Q1 Timing Diagram. Please show attached file. When device is shutdown, VIN, EN, VLDOIN and VREFIN is OFF at same time. Is there any problem about reliability of device? ex. not recover after power reboot.

    Best regard,

    tateo

    TPS51200Q1_Timing diagram_rev4.pptx

  • Tateo san,

    Yes, they could be turned off at the same time. And TPS51200-Q1 device is OK for that operation.
    When all these 4 power lanes are powered off, device will be shut down immediately, and no current or voltage output.

    Best regards,
    Jason Liu
  • Thank you for your help. My customer understand shutdown sequencing.
    But my customer wants to know about UVLO protection. Because my customer is thinking when VIN=0V, UVLO prevents unexpected like spike would occur at startup and shutdown.

    - When VIN=0V and VLDOIN is biased at shutdown and startup, does UVLO prevents unexpected like spike would occur?
      Please tell me detail about UVLO protection at two case.

    Best regards,

    tateo

  • Yes, that's right.
    For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is a non-latch protection.

    Best regards,
    Jason Liu
  • Thank you for your reply. If UVLO power off VO and REFOUT, my customer wonder why when VIN=0V, the device can not control the LDO output stage which is biased by VLDOIN.
    Because VIN=0V is lower than the UVLO threshold voltage. My customer is thinking the device would be OK that VIN=0V and VLDOIN is powered up.

    Best regards,

    tateo

  • But could you tell me why does customer want to set condition to "VIN=0V and VLDOIN is powered up"? For some special application?

    Best regards,
    Jason Liu
  • It is particular situation. My customer has two projects. He should design same circuit between two project. There are some constraints. Circuit is attached file.

    Now my customer is using load switch for timing control(VIN and EN is ON -> VLDOIN is ON). But he wants to reduce the number of parts. He is thinking if UVLO prevents unexpected like spike would occur, he can reduce load switch. Keypoint is UVLO and reliability.

     - When VIN=0V and VLDOIN is biased at startup, can UVLO prevent unexpected like spike would occur?

     - If VLDOIN and REFIN is ON before VIN and EN is ON, is there any problem about reliability of device?

    Sorry to trouble you, but could you give your feedback about this.

    Best regards,

    tateo

    TPS51200Q1_Timing diagram_rev5.pptx

  • Hi Tateo,

    We cannot guarantee the IC performance if using with this power up sequence. Something unexpected may happen when the VIN/EN ramping up to around UVLO. Spikes or inrush current may occur at this time, which could break the device or the load.

    We suggest customer follow the recommended sequence in the datasheet.

    Best regards,
    Jason Liu
  • Thank you for your reply. I'll suggest customer follow the recommended sequence in the datasheet.

    But my customer can't understand UVLO protection. He expect to prevent something of a problem at startup and shutdown. He is worried about using this device.
    Please explain more detail about why UVLO is unable to prevent something of a problem.

    Best regards,

    tateo

  • Hi Tateo,

    As you know, usually there is a min value and a max value for the UVLO.
    IC will be shutdown when input voltage is smaller than UVLO min value, powered up when input voltage is larger than UVLO max value, uncertain when input voltage is between the min and max value.

    We cannot make sure the work status when VIN is between the min and max value, and some glitch may be caused when VLDOIN and REFIN are already powered up at this time, which could cause unexpected results.

    So we suggest VLDOIN and REFIN should be powered up after at least VIN is stable.

    Best regards,
    Jason LIU