How to tell if the TPS65381 caused a reset

Hi David,

Sorry about the delay but I had to do some research with our systems engineer to get a good answer on this one. These monitoring techniques should not only let you know if the cause was the WDT but some other causes of RESET or transition to STANBY state (which then also would reset the MCU).

Since there is no direct method to determine if a reset from the TPS65381 was caused by a watchdog timer failure, an indirect method must be used.  Such a is outlined below. The MCU application should track and observe the following to determine the possible reset cause.

• WD Fail Count

  • Track WD Fail count to detect when it reaches count of 5 and latch it, or

  • Track/monitor EN_DRV output being disabled (driven low) when while device remains in ACTIVE state and latch it

    NOTE: within two + one WD non serviced WD cycles after the WD Fail count reaches 5, the WD reset occurs (if WD Reset is enabled)

    NOTE: the software cannot rely on WDE status bit since does not remain latched after reset event

• Device Error count

  • If device error count remained the same as the count prior the reset event, device did not transition through SAFE state to RESET state

  • Observe and latch every time device enters SAFE state if SAFE state TO is disabled.

• VDD5 Over-Temp

  • Check status bit (it remains latched after reset event)

• VBAT Over-Voltage

  • In most applications, VBAT is monitored by MCU ADC and system can check if VABT is approaching too high level

  • The TPS65381 de-glitch time for VBAT OV event should be long enough to assure the MCU could latch the over voltage event prior to TPS65381 asserting RESET low due to VBAT OV.

• VDD1 Under-Voltage

  • Assuming VDD1 is used for the MCU core supply, some MCUs integrate an internal ‘crude’ comparator with its status latched to determine this cause of reset.

  • NOTE: application cannot rely on TPS65381 VDD1_UV status bit since it may not remain latched after reset event

• VDD3/5 Under Voltage

  • Can be monitored by MCU ADC as long as it is not supply for MCU core and/or supply for MCU ADC

  • NOTE: application cannot rely on VDD3/5_UV status bit since it may not remain latched after reset event

Also, since some events could cause the TPS65381 to change to STAND-BY state where a RESET (active low) would occur that the as well, MCU can monitor the following to determine this transition:

• LOCLK status flag

• VDD3/5_OT status flag

• MCU can detect if IGN was driven low

• MCU can detect when CAN WU latch is cleared (done through MCU initiated SPI command)

• MCU can detect VBAT_UV (VBAT should always monitored on the system level to detect different VBAT voltage levels – different VBAT voltage levels drives different system operating modes)

Best Regards,

Scott