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TPS65381-Q1 VDD1_OV and VDD1_UV

Other Parts Discussed in Thread: TPS65381-Q1

Hi
 
 My customer is using TPS65381-Q1.
 They is using VDD1 as 1.2V out setting.
 They have issue.

 Error flag of VDD1_OV and VDD1_UV doesn't occuer on error situation.
 They has tested system with TPS65381-Q1.
 It is connected the programable voltage of unipolar type to VDD1 pin.
 For VDD1_UV check, VDD1 is became to 1.1V by the external programable voltage.
 And for VDD_OV check, VDD1 is became to 1.5V by the external programable voltage.

 But VDD1_OV and VDD1_UV of VMON_STAT_2 register as error flag doesn't become "1" .   
 
 Could you check the VDD1 error function?

 By the way, VDD3_OV/UV and VDD5_OV/UV succeeded in a check by this way.

Thanks
Shimizu

  • Hi Shimizu-san,

    First, did they enable the VDD1 OV and UV monitoring for VDD1? It is off by default to allow start up timing differences on VDD1 due to the external FET impacts and also allows for use of VDD1 monitoring with an external DCDC converter instead of the VDD1 LDO controller so you have to enable the UV and OV monitoring via the nMASK_VDD1_UV_OV bit in the DV_CFG1 register?

    Can you clarify how they are forcing the UV and OV conditions to occur. I don't understand what they mean by external programmable voltage, is this an external voltage supply that can sink/source current adequate to force the UV or OV volgate on VDD1?

    - Scott
  • Hi Scott-san,

    Thank you for your support.
    I'm sorry. I mistook to confirm nMASK_VDD1_UV_OV bit.
    My customer was able to confirm OV and UV of VDD1 by setting nMASK_VDD1_UV_OV bit.

    And we have a issue of following.
    Over voltage value of VDD1 is over than spec value in datasheet.
    (Under voltage is OK)
    Customer confirmed OV by becoming low of ENDRV signal.

    Rsence=39-ohm/75-ohm
    [Measured value]
     TYP 1.220[V]
     UV 1.158[V] -> 0.949(OK)
     OV 1.314[V] -> 1.077(NG)
            VDD1_SENSE=0.856[V](1.07)   
     
    Could you advice me for issue?
    I will send you customer's circuit and waveform VDD1/VDD1_VSENSE/ENDRV) through TIJ menber.
    (Include the circuit of "external programmable voltage")

    Thanks,
    Shimizu
  • Hi Shimizu-san,

    I received the waveform and schematic.I believe I understand where the misunderstanding with the customer is, but I want to double check with the systems engineer on this device so please give me a day or two.

    Thanks,

    Scott

  • Hi Scott-san

    Thank you for your support.
    How is the progress?

    Thanks
    Shimizu
  • Hi Shimizu-san,

    We are double checking all the assumptions on this topic. It is not clearly specified what is and is not included in the ratio to VDD1. It is clear the tollerance of the external resistors are not included, but would impact the VDD1 voltage, since VDD1 OV or UV is detected at the VDD1_Sense pin. We are double checking if the +/-2% tollerance on the VDD1_Sense also needs to be included or not with the VDD1_UV or UVDD1_OV ratio. We will need some more days to go back through all the documentation and assumptions on this parameter.

    Scott
  • Hi Scott-san

    Thank you for your support.
    How is the progress?
    Please let us know when you can send the information about this issue.

    Thanks
    Shimizu
  • Hi Shimizu-san,

    Sorry for the delay but we wanted to be sure in the response.  I will send a response to the TI team that supports you to close this out.

    Scott 

  • Hi Scott-san

    Thank you for your support.
    I understood your situation.

    Thanks
    Shimizu
  • Hello Scott,

    do you have any news on this issue?

    We have problems calculating the tolerances of VDD1_OV /VDD1_UV thresholds, too.

    Regards,
    Thomas
  • Hi Thomas,

    The calculations of the tollerance of the device itself are a ratio of the VDD1_SENSE, relative to the 0.8V nominal that is expected on the VDD1_SENSE pin. So the device will have the UV and OV tollerances listed in the datasheet for UV and OV with respect to the 0.8V (or VDD1). What is not included in this tollerance it he external resistor divider. Any tollerance on the resistor divider will also impact the UV / OV thresholds.

    Scott
  • Dear Sirs,

    I want to clarify, how the question about the calculation of the VDD1_SENSE tolerances arose.

    We have a question about the tolerances in the generation and monitoring of the voltage VDD1.

    Please see our interpretation of the datasheet below:

    The VDD1 is generated by an internal regulator with an external FET. The reference voltage VMAIN_BG is used to set the voltage level via the external resistive voltage divider at VDD1_SENSE.

    The Table 5-1 says in the row “VDD1”: Created from reference VMAIN_BG.

    The voltage VDD1 is monitored at the pin VDD1_SENSE, which is the same pin as the feedback reference, so there is one internal circuit to regulate the voltage and another internal circuit which monitors the voltage at the same pin.

    The VDD1_SENSE is monitored referenced to the reference voltage VMON_BG. This is stated in the aforementioned Table 5-1, row “VDD1”: Monitored against reference VMON_BG.

    The reference voltages are independent bandgap voltages internal to the IC. The tolerances of the voltages are given as 2.5V +-2%. (Table 5-1, rows MAIN_BG and VMON_BG).

    The undervoltage level is given in Table 5-1 in the range: UV = (0.94 .. 0.97) * VDD1.

    As the factors given under “4.5 Electrical Characteristic” point 6.16 are (0.94 .. 0.98) we take the more pessimistic one (0.98) especially as the factor in the “Electrical Characteristic” has been changed from datasheet version C to D to 0.98 (from the former 0.97).

    Now, if the tolerances of the independent reference voltages MAIN_BG and VMON_BG are +-2%, than one could be 2% high, while the other is 2% low and the undervoltage level UV is reached just by the opposing tolerances. There is no headroom for additional error for the external resitive voltage divider or the internal divider from 2.5V to 0.8V.

    The bias voltage at the pin VDD1_SENSE is 0.8V (nominal), so there is some kind of voltage divider to divide the 2.5V to the value of 0.8V. The tolerance of the voltage divider for the generation of the VDD1 is given under “Electrical Characterisitcs” point 4.2 as (-1%) to (+2%). Here arises the question, how the VDD1 reference voltage (0.8V) can have tighter tolerances than the reference VMAIN_BG (-2%, +2%).

    Is this interpretation of the datasheet correct? It is safe to assume, that no incorrect UV alarm occurs due to internal tolerances?

    Thanks in advance for your help,

    Regards,

    Volker

  • Hello Volker,

    Let me help clarify your points and questions.  I will leave your statements in black font and respond in blue font.

    Q1:  The VDD1 is generated by an internal regulator with an external FET. The reference voltage VMAIN_BG is used to set the voltage level via the external resistive voltage divider at VDD1_SENSE.   The Table 5-1 says in the row “VDD1”: Created from reference VMAIN_BG.

    A1: Yes, VDD1 regulator is an LDO controller using and external FET with the feedback of the external regulated voltage sensed on the VDD1_SENSE pin.  The regulation loop reference is generated by the main bandgap reference (MAIN_BG also called BANDGAP_REF1). 

    Q2:  The voltage VDD1 is monitored at the pin VDD1_SENSE, which is the same pin as the feedback reference, so there is one internal circuit to regulate the voltage and another internal circuit which monitors the voltage at the same pin.  The VDD1_SENSE is monitored referenced to the reference voltage VMON_BG. This is stated in the aforementioned Table 5-1, row “VDD1”: Monitored against reference VMON_BG.

    A2:  Yes, VDD1 voltage is monitored on VDD1_SENSE as well.  There are separate independent circuits internal to the device using the VDD1_SENSE pin.  One of these circuits is the regulation loop and uses this pin as the feedback reference pin and the main bandgap MAIN_BG. The second and independent circuit is the voltage monitoring for overvoltage (OV) and undervoltage (UV).  This voltage monitor is derived from a 2nd independent bandgap, VMON_BG or BANDGAP_REF2.  Thus the voltage regulation circuit and the voltage monitor circuit are derived from separate bandgap references.  If you look into the functional block diagram in section 5.2 of the datasheet you will also see the supplies to the MAIN_BG (VBATP) and VMON_BG (VBAT_SAFING) are independent, thus separating the regulation circuit from the monitoring circuit.

    Q3: The reference voltages are independent bandgap voltages internal to the IC. The tolerances of the voltages are given as 2.5V +-2%. (Table 5-1, rows MAIN_BG and VMON_BG). The undervoltage level is given in Table 5-1 in the range: UV = (0.94 .. 0.97) * VDD1.  As the factors given under “4.5 Electrical Characteristic” point 6.16 are (0.94 .. 0.98) we take the more pessimistic one (0.98) especially as the factor in the “Electrical Characteristic” has been changed from datasheet version C to D to 0.98 (from the former 0.97).

    A3:  This row Table 5-1 needs to be updated to UV = (0.94 .. 0.98) * VDD1.   This value was updated in the electrical parameters which are the actual spec of the device, but during that update the line in Table 5-1 was missed.  There is a revision of the DS in work to correct this.  Similarly in Table 5-2, D1.15, VDD1_UV will be updated as well to 0.94 to 0.98.   So that all the ratios are 0.94 to 0.98.  Taking 0.98 is the correct assumption. 

    Q4:   Now, if the tolerances of the independent reference voltages MAIN_BG and VMON_BG are +-2%, than one could be 2% high, while the other is 2% low and the undervoltage level UV is reached just by the opposing tolerances. There is no headroom for additional error for the external resistive voltage divider or the internal divider from 2.5V to 0.8V. The bias voltage at the pin VDD1_SENSE is 0.8V (nominal), so there is some kind of voltage divider to divide the 2.5V to the value of 0.8V. The tolerance of the voltage divider for the generation of the VDD1 is given under “Electrical Characteristics” point 4.2 as (-1%) to (+2%). Here arises the question, how the VDD1 reference voltage (0.8V) can have tighter tolerances than the reference VMAIN_BG (-2%, +2%).

    A4:  This is not the correct direct interpretation on the margins for VDD1.  The Bandgap tolerances are listed in those tables are include the inaccuracies added to buffering circuits when they are read out via the diagnostic output pin.  However the electrical specification of the device is given only in the electrical characteristics portion of the datasheet.  The bandgaps are not directly specified here, but the end product of their reference is specified, such as a regulator tolerance.  As you have noted the VDD1 reference voltage for the regulation tolerance of VDD1 was actually tightened to -1% to +2% (originally +/-2%).  This was done intentionally and based on characterization data and production test limits to ensure there is still at least 1% margin between the minimum regulation of the device and the maximum UV detection of the device was raised from 0.97 to 0.98.  This leaves 1% margin between the two values for the error or tolerance of the external resistor divider. 

    Q5:  Is this interpretation of the datasheet correct? It is safe to assume, that no incorrect UV alarm occurs due to internal tolerances?

    A5:  As noted there is minor interpretation change, but there is no incorrect UV alarm due to internal tolerances. A visual way to see the device tolerances on this topic is below which still leave 1% gap between the regulation and UV or OV detection at device level for external impacts such as the resistor divider, PCB, ripple is shown below.  In addition there is VDDx_deglitch on the UV and OV monitoring to prevent transient noise from causing a UV or OV alarm. 

     

    Best Regards,

    Scott

  • Hello Scott,

    thank you very much for the detailed explanation!

    I think, this resolves our concerns.

    I would to suggest to emphasis in the data sheet, that the tolerances for VDD1_SENSE are related to the tested values instead of calculated.

    Another point is the bias current of the VDD1_SENSE pin. In another discussion the current was specified as 8,5 uA.

    I would suggest to specify the bias current in the data sheet, too.

    Regards,

    Volker