One of the entry condition for the PFM mode is that the duration when both high-side and low-side FETs are off needs to exceed 60% of the clock period as explained in the datasheet.
To be accurate, when one channel’s high/low-side FETs are off for over 60% of the clock period, this channel will enters the PFM mode, even if another channel operates in CCM
(assuming the other entry conditions are satisfied.), correct?
Regards,
Takamune Suzuki