PGA450-Q1 measurement with interrapt

This source code for meashure on 58kHz and making output DAC signal at Testo_A pin.

void timer1_ISR (void) interrupt 3 using 2 {

ET1 = 0;

DOWNSAMPLE = 0x1E;

BPF_B1_MSB = 0x03;
BPF_B1_LSB = 0x2D;
BPF_A2_MSB = 0xF4;
BPF_A2_LSB = 0xE6;
BPF_A3_MSB = 0xF9;
BPF_A3_LSB = 0xA5;
LPF_B1_MSB = 0x24;
LPF_B1_LSB = 0x4E;
LPF_A2_MSB = 0x37;
LPF_A2_LSB = 0x64;


PULSE_CNTA = 0x09; // # pulses during burst
BLANKING_TIMER = 0xFF; // Waits #*16 uS after ECHO_EN = 1 to fill up FIFO (Ignores very close range data)
FIFO_CTRL = 0x07; // NO FIFO Rollover, [10:3] mode
CONTROL_1 = 0x01; // SAT threshold 300mV, LNA Gain = 400 V/V

FifoWritePointer.u16 = 0;
FRT_T1.u16 = 0;
FRT_T2.u16 = 0;
TimeOfFlight.u16 = 0;
MaskEcho = 0;
DetectIndex = 0;

PWR_MODE = 0x03; // VREG_EN (D1)=1, ACTIVE_EN (D0)=1, ready for ultrasonic burst
EN_CTRL = 0x00; // Clear FIFO memory before burst
BURST_MODE = 0x00; // Push Pull mode
BURST_ONA_MSB = 0x00;
BURST_ONA_LSB = 0xC8; // ON Time = 8.6us 16MHz/40KHz/2
BURST_OFFA_MSB = 0x00;
BURST_OFFA_LSB = 0xC8; // OFF Time = 8.6us
DEADTIME = 0x05; // Dead time between burst phases to limit shoot through current
SAT_DEGLITCH = 0x09; // 2us per count || 1/58kHz (17.2uS)

while(STATUS2 & 0x01 == 0){}// Wait for VREG to be ready
EN_CTRL = 0x85; // Enable Burst and saturation check, as well as log Free Running Timer

//Record time
FRT_T1.u8[0]=FRT_MSB;
FRT_T1.u8[1]=FRT_LSB;

while(STATUS2 & 0x02 == 0){} // wait for decay done to be set
// If needed, user can check for the decay time capture here to check for an effective burst as a diagnostic

PWR_MODE = 0x01; // VREG disabled for better noise, ACTIVE mode remains enabled
EN_CTRL = 0x0C; // Enable Echo
EA = 0; // Disable interrupts during echo processing

for(lcv=3;lcv<767;lcv++){
// Read FIFO Pointer coherently
while ( lcv >= FifoWritePointer.u16 ){
FifoWritePointer.u8[0] = FIFO_POINTER_MSB;
FifoWritePointer.u8[1] = FIFO_POINTER_LSB;
if ( FifoWritePointer.u8[0] != FIFO_POINTER_MSB ) { // Check if coherent
FifoWritePointer.u8[0] = FIFO_POINTER_MSB;
FifoWritePointer.u8[1] = FIFO_POINTER_LSB;
}
}
}

PWR_MODE = 0x02; // VREG_EN (D1)=1, ACTIVE_EN (D0)=0, ready for ultrasonic burst
EN_CTRL = 0x00; // Clear all enables
EA = 1;

TL1 = 0x00; // Clear timer1 counter
TH1 = 0x00; // Clear timer1 counter
ET1 = 1;

}

Sergey,
Since you are using a Timer1 based interrupt, TCON and TMOD must be used to set the mode of operation and to control the running and interrupt generation of the timer/counters. The two Timer overflow interrupts, TF0 and TF1, are set whenever timer 0 or timer 1 respectively roll-over to zero. The states of these interrupts are also stored in the TCON register. TF0 and TF1 are automatically cleared
by hardware on entry to the corresponding interrupt service routine. Be sure to initialize Timer1 as in "PGA450_init.c" of the PGA450Q1EVM Firmware.

TMOD = TMOD | 0x20; // Timer1 , 8bit mode of operation
TL1 = 0x00; // Clear timer1 counter low byte
TH1 = 0x00; // Clear timer1 counter high byte

You have already considered to Enable Timer 1 overflow interrupt via bit ET1 = 1.
Are you unable to access your ISR?