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Abnormal SW of TPS57160-Q1

Other Parts Discussed in Thread: TPS57160-Q1

Dear Support team

My customer try to evaluate prototype board using TPS57160-Q1.

On their board SW duty becomes low periodically like sub-harmonic oscillations.(Please see attached file)

I guess this is caused by pattern layout.

Please give advice about root cause and pattern layout.

1016.TPS57160 Question.xlsx

Regards

Tomohiro Nagasawa

  • TPS57160_Duty_Cycle_20Vin_12V_Vout_2MHz_200mA_load.xlsx

    Hello Nagasawa-san,

    I quickly checked it in the lab and i did not see the issue on our EVM (standard EVM schematics from TI website configured to 12V output, 200mA load current). See the attached document.

    I looked at the layout and definitely there is a scope for improvement. Can you ask them to look in to the "layout guidelines" section of the datasheet and ask them to improve it?

    If they can quickly check the by shorting the series diode at PH node and removing pull down resistor at PH node to confirm that this is not causing this issue.

    Why do they have such a high inductor value (68uH is shown in this excel sheet)?

    Regards,

    Murthy

  • Hello Murthy-san

    Thank you for quick response and send your report !

    Because it is necessary to avoid DCM, they use  68uH inductor. (I'm sorry in insufficient explanation)

    I confirmed behavior using  EVM and Webench.

    And  the phenomenon of the customer was reproduced. (See attached file)

    Please confirm below questions.

    Your prompt response will be  highly appreciated.

    1.What is the cause of this behavior?

    2. Could you teach schematic of your report?

    Thanks

    Best Regards

    Tomohiro Nagasawa

    Waveform (HPA230 EVM).xlsx

  • Hello Nagasawa-san,

    I checked with standard EVM schematics by changing RT=53K ohm and adjusting output voltage to 12V. In this case i have used 4.7uH inductor and i do not see the issue. Is it possible for you to quickly check by replacing inductor to 4.7uH and give me the feedback?

    http://www.ti.com/lit/ug/slvua80/slvua80.pdf

    In the mean time, i will check why device is showing this behaviour with large inductor.

    Regards,

    Murthy

     

  • Hello Murthy-san

    Thank you for quick response.(Sorry for delay response.)

    I add result of L=4.7uH and 15uH waveform.(See attached file)

    This behavior is not seen when L=4.7uH .And device enter DCM instead.

    If you have any other solution, Please teach me.

     

    Thanks

    Best Regards

    Tomohiro Nagasawa

    Waveform (HPA230 EVM)_2.xlsx

  • Hello Nagasawa-san,
    I tried to check in the lab again with 57uF output capacitor (close to your value), with 4.7uH inductor, it works fine and device does not get in to the DCM mode also. Anyhow, i have asked fruther support from design team and let you know once i have some update from design team.
    Regards,Murthy
  • Hello Murthy-san

    Thank you for strong support.

    We'd appreciate it if you could reply to me as soon as you can.

    Thanks

    Best Regards

    Tomohiro Nagasawa

  • Hello Nagasawa-san,

    I got the feedback from design team. Duty cycle variation is due to the high noise on the PH, Vin, GND pins and the low slope of the i_inductor. The higher the L, the higher the noise on the PH pin and the lower the slope of the i_inductor. The work around is to reduce the L. For, FS=2MHz, I_load = 0.2A and Vout=12v with 50% duty cycle, you can go as low as 7.5uH before hitting the DCM. However, smaller L will increase the Vout ripple but by using large C, Vout ripple can be reduced.

    So, i would suggest to do the work around on the customer board as this could vary depending on the layout.

    Hope this helps.

    Regards,

    Murthy

  • Hello Murthy-san

     

    Thank you for strong support.

    Well, Could you advice about  their layout ?(see attached pattern layout sheet)

    Sorry for luck of study.  Why does higher L and lower slope have high noise?

     

    Thanks

    Best Regards

    Tomohiro Nagasawa

     

    1234.1016.TPS57160 Question.xlsx

  • Hello Nagasawa-san,

    Noise = V_noise =L*(di_noise/dt): the higher the L, the higher the noise.

    Lower the slope of the i_inductor, the lower the SNR (SNR = k*( slope of the i_inductor)/V_noise).

    Hope this clarifies your doubt. Regarding the layout review, i will give you a feedback by tomorrow.

    Regards,

    Murthy

     

  • Hello Murthy-san

    Thank you for kindly support.

    We are waiting for your feedbuck.

     

    Regards

    Tomohiro Nagasawa

  • Hello Nagasawa-san,

    Please find the my observations below regarding the layout.

    * It is very important that GND connections of input filter capacitor, output filter capacitor and catch diode are made as short as possible to reduce the switching loop. So, I think significant improvement can be done in the layout to minimize this loop, but they have to rework on the layout. I have marked my observations in the attached excel sheet.

    * If they do not want to do large layout change, then they can atleast flip the catch diode 180 degree and make the GND connection close to the device. With this approach, switching loop is improved, but still sensitive components/traces like compensation and feedback network is close to the switching area and they have to make little more space there and try to schield them from noise.1234.1016.TPS57160 Question_reviewed_murthy.xlsx

    Regards,

    Murthy

     

  • Hello Murthy-san

    Thank you for sending reviewed file.

     I'm trying to advise them according to this file.

     

    Regareds

    Tomohiro Nagasawa

  • Hello Murthy-san

    Thank you for kindly support.

    I have discussed with customer ,and I'm going to permit entering DCM because they could not rework layout change.  

    I guess the demerit of DCM to be noise and accuracy of output voltage.  

    Could you estimate the accuracy of output voltage  is how much in DCM?

    And they have one question. Why is this befavior(duty cycle variation) easy to happen when Vin is low?

     

    Regards

    Tomohiro Nagasawa

  • Hello Nagasawa-san,
    In DCM mode, they may be slight increase in output current ripple and i didnt see much difference in output voltage ripple. Please see Figure 56. Output Ripple, DCM in the datasheet for the plot.
    Regarding your question on why this happens when Vin is low: I think I did not understand it very correctly. But problem of duty cycle variation in this case is mostly because of the noise (poor layout) and not because of lower Vin voltage.
    Regards,Murthy