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TPS65381-Q1 WD timeoiut

Mitsuharu Iwasaki55
Intellectual 750 points
Other Parts Discussed in Thread: TPS65381-Q1

Hello,

When WDT_FAIL_CNT reaches 7 during ACTIVE state and WD_RST_EN=1, TPS65381-Q1 goes to RESET state based on PRIOR Ⅱ.

It's wriiten on page 65 in the DM. But TPS65381-Q1 can go to DIAGNOSTIC state through SATNBY -> RESET.

How can a processor realize whether TPS65381 is from ACTIVE or STANBY?

Best Regards,

Mitsuharu Iwasaki 

  • 0
    TI__Mastermind 20580 points
    The processor can read the device state from SAFETY_STAT_5 Register. FSM[2:0] or bits D[2:0] hold the device state.

    To clarify a little, when WDT_FAIL_CNT reaches 7 and WD_RST_EN = 1, on the next bad event in the watchdog timer the device will go through the RESET state.

    Best Regards,
    Scott
  • 0 in reply to Scott Monroe
    Intellectual 750 points
    Scott,

    Thank you for replying.
    When WDT_FAIL_CNT reaches 7 and WD_RST_EN = 1, on the next bad event in the watchdog timer the device will go through the RESET state.
    But after Power-up, PMIC goes to RESET through STANBY. How can a external procesoor understand that PMIC comes from ACTIVE->RESET by WD_FAIL_CNT error or PMIC comes from SATNBY->RESET by Power-up?

    Regrads.,
    Mitsuharu Iwasaki
  • 0 in reply to Mitsuharu Iwasaki55
    TI__Mastermind 20580 points

    Hi Iwasaki-san,

    There isn't a direct way to tell if the watchdog was the cause of the reset. See the following E2E post that outlines how you can track various possible RESET causing events and determine if it was the watchdog or some other event causing RESET:

    Scott