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TPS65381-Q1 Watchdog

WS Lee
Intellectual 1935 points

Hi team,

 

Here are some questions related to Watchdog. After looking for it, please reply to me.

 

The following is the explanation related to Watchdog and based on this, Watchdog fail count is independent on Watchdog Reset Enable. When Watchdog Fail Count reaches to “7”, if Watchdog Reset Enable is set to “High”, it seems to be reset. Is it right?  

====

"The watchdog fail counter operates independently of the state of the watchdog reset configuration bit (bit 3), WD_RST_EN, in the SAFETY_FUNC_CFG register."

"If the watchdog fail counter is at seven when WD_RST_EN is set to one, the device will immediately enter the RESET state without requiring another bad event."

====

Default time for Watchdog Open/Close is each as below. 

WDT_WIN1_CFG = 0x7F * 0.55ms = 68.85ms

WDT_WIN1_CFG = 0x18 * 0.55ms = 13.2ms

 

After reset, the time which Watchdog Fail Count is from default “5” to “7” is 164.1ms and if watchdog is not response in this time and Watchdog Reset Enable is set to”High”, does reset occur? Is it right?

 

If yes, due to MCU initialization delay time, during this time, when Watchdog is not set, if Watchdog Reset enable, Reset occurs. Is there any way to avoid this? 

Is it not possible to initialize Watchdog Fail Count during Diagnostic state?

 

Thanks,

WS

  • 0
    TI__Mastermind 20580 points

    Hi WS,

    Q1:  Default time for Watchdog Open/Close is each as below. 

    A1:  These are not correct formulas, make sure to use the Rev F datasheet on www.ti.com.  This datasheet also clarifies the window and watchdog sequence (WIN1+WIN2) timing. 

     

    Q2:  WDT_WIN1_CFG = 0x7F * 0.55ms = 68.85ms

    A2:  There is a tolerance on the timing for the two windows

        tWIN1_MIN = ((RT[6:0] - 1) × 0.55 × 0.95) ms

        tWIN1_MAX = (RT [6:0] × 0.55 × 1.05) ms

     

        with the default window setting of 0x7F the window 1 will be between 65.84ms and 73.34

     

    Q3: WDT_WIN2_CFG = 0x18 * 0.55ms = 13.2ms   (actual re-initialized default time is 0x1F not 0x18)

    A3:   tWIN2_MIN = ((RW[4:0] + 1) × 0.55 × 0.95) ms

            tWIN2_MAX = ((RW[4:0] + 1) × 0.55 × 1.05) ms

     

           with the default window setting of 0x18 the window 2 will be between 13.06 and 14.44 ms.

     

    Also, the WIN1 and WIN2_CFG registers will not be re-initialized after RESET so the values (timing) will match what they were programmed them to prior to RESET. 

     

    Q4:   After reset, the time which Watchdog Fail Count is from default “5” to “7” is 164.1ms and if watchdog is not response in this time and Watchdog Reset Enable is set to”High”, does reset occur? Is it right?

    A4:  After RESET when the device enters DIAGNOSTIC the watchdog fail count is re-initialized to 5.  If the MCU does not respond to the TPS65381 watchdog and WD_RST_EN remains HIGH, when the WD_FAIL_CNT reaches 7 + 1 another RESET will be issued.  Using default settings for WIN1_CFG and WIN2_CFG this would be between 237 and 263 ms after NRES was released.  If the customer has programmed the WD_WINx_CFG to lower values (shorter times) then the next RESET will occur sooner.   In other words, the MCU must synchronize to the TPS65381 and start decrementing the WD_FAIL_CNT within 3 “timeout”events or simply clear WD_RST_EN in that amount of time and synchronize without the time restriction from the watchdog. Once the synchronization has occurred and the WD_FAIL_CNT is decremented properly WD_RST_EN is then reset to 1.    

     

    It is recommended that one of the first things to do in the boot (or re-boot) sequence on the MCU is to clear WD_RST_EN.  This way the MCU can synchronize to the TPS65381 watchdog in DIAGNOSTIC without risk of another RESET.    

     

    Q5:  If yes, due to MCU initialization delay time, during this time, when Watchdog is not set, if Watchdog Reset enable, Reset occurs. Is there any way to avoid this? 

    Is it not possible to initialize Watchdog Fail Count during Diagnostic state?

     

    A5:   It is recommended that one of the first things to do in the boot (or re-boot) sequence on the MCU is to clear WD_RST_EN.  This way the MCU can synchronize to the TPS65381 watchdog in DIAGNOSTIC without risk of another RESET.    

    It is not possible to write to the watchdog fail counter, if the MCU could write to it, clearing WD_RST_EN is just as effective to prevent another RESET. 

    Best Regards,

    Scott