The mode of operation of TPS43336-Q1

Tokomoto-san,
correct. In fact, even if DIV is high, the boost will be disabled in case both bucks are turned off, so for all conditions
ENA=Low,ENB=Low,ENC=H,SYNC=X, DIV=X
DIV=high will prevent the bucks from operation in low power mode, but if they are off, the boost will be off as well.
This applies also in case there is a load (in addition to BuckA and BuckB) on VIN.
Note: in case the supply voltage drops below the boost unlock-threshold (8.2V min, 8.5V typ, 8.8V max) while both bucks are off (and thus the boost is off), the supply voltage will need to exceed the boost-unlock-threshold before the boost will get active or can be activated.
Best regards,
Frank

Tokomoto-san,
We do not specify the latency between ENx and the actual start of the ramp.
I measured on a TPS4333x-EVM:
BuckA:
If Buck B is enabled, BuckA starts its ramp ~65us after ENA goes high.
If Buck B is disabled, BuckA starts its ramp ~1.15ms after ENA goes high.

BuckB:
If Buck A is enabled, BuckB starts its ramp ~125us after ENB goes high.
If Buck A is disabled, BuckB starts its ramp ~1.2ms after ENB goes high.

If both, BuckA and BuckB get enabled simultaneously, BuckB ramps ~1.15ms, BuckA ramps ~1.2ms after ENx go high.

The reason for the difference is that if no Buck is enabled, VREG is powered off. If any buck is enabled, the internal logic needs to be supplied first (VREG ramping and getting stable), while it is already available if the other buck was already on.

Note, in any case, in addition to the delay time, there will be the soft-start time, which is set by the capacitor on SSA resp. SSB.

Regarding the behavior of GC2:
Not sure about the exact conditions "ENC=Hi" would mean the boost is enabled, while "Boost-controller=disabled" says the opposite.
If both bucks are off, the boost is off as well, which is the case if ENA=Low and ENB is pulled high only during the test.
If the part needs boosting when a Buck is turned on (here the case as DIV=Hi means 10V boost output, while VBAT=7V), the boost will not turn on until VBAT passes the boost-unlock-threshold (~8.5Vtyp).
If the bucks are only off briefly and the output capacitors of the Boost are still charged, the boost may be able to restart, but this is a measurement option only, as the off-time in the actual application is likely not known.
In your case, GC2=Hi as long as the boost is off (because both, ENA and ENB are low). If one is turned on, the boost tries to activate itself, thus GC2 goes low to disable the bypass). The outptu voltage can stillbe maintained, as VBAT is sufficiently high for the internal regulator and the 3.3V output voltage. However, if VBAT keeps falling and/or a higher output voltage needs to be maintained, one Buck needs to be kept enabled during a drop in VBAT in order to keep the boost alive.
One option to support VBAT=7V and booster can still activate is the TPS43333-Q1, which has a reduced boost-unlock-threshold of 6.5V (note, this is at IC-pin, e.g. a drop over reverse polarity protection needs to be considered.

Best regards,
Frank