Automotive

Forum Post: RE: SN65HVDA100-Q1 Question about dominant output

John Griffith — Tue, 18 Jun 2013 14:04:00 GMT

Hi Hide,

If I am understanding you correctly, when you are changing the state of the EN pin from low to high, the TXD pin is low. This will always result in the bus being driven dominant. The bus will remain dominant until either the TXD pin is pulled high, or the dominant state timer triggers (anywhere between 20 and 80ms).

You will need to ensure that the TXD pin is high before switching into normal mode if you want to avoid a dominant signal being driven on the bus.

Please let me know if you have any other questions.

John

Forum Post: TL720M05-Q1 Question about Input Voltage Drop

HIDE — Tue, 18 Jun 2013 09:02:00 GMT

Hi,

I have some questions about Input Voltage Drop on TL720M05-Q1.

This application is connecting 16 LDO Units in parallel like below;

(Power: +17V)

(1) Power ON with connecting 16 LDO units, but input voltage fall to 3V and all of units don't work.

(2) Remove LDO unit one by one. When connecting 6 LDO Units, input voltage raise to 14V and output voltage reach to 5V.

(3) Add LDO unit one by one. Work correctly until 11 units connection. When connecting 12 unit, input voltage fall to 3V and all of units don't work.

* I checked the power supply, but there is no probrem without current limit.

Can you please advise me why unstable behavior happen? Is there any protection work? Is there any solution to solve this phenomenon?

Thanks in advance.

Hide

Forum Post: RE: TL720M05-Q1 Output current limit specification

David Xu1 — Tue, 18 Jun 2013 01:44:00 GMT

Hi Atsushi-san,

The current limit variation is mainly caused by process variation, the temp vs. current limit graph in the datasheet is drawn based on the test data on few devices which represent the typical value of most devices. In term of more accurate current limit, a trim module is needed which will lead to larger die size. For this device, there are not any trim module, so the current limit range is large.

Best regards

David Xu

Forum Post: The ultrasonic sensor for PGA450-Q1

Atsushi — Mon, 17 Jun 2013 09:16:00 GMT

I have a question of the ultrasonic sensor for PGA450-Q1.

We can use the frequency range 40kHz to 70kHz for Digital path.

So, usually, the frequency of the ultrasonic sensor should be 40kHz to 70kHz.

Is it correnct?

And I wolud like to confirm how much can PGA450-Q1 drive the frequency of the ultrasonic sensor

even if PGA450-Q1 can not receive the signal.

Best regards,

Atsushi Yamauchi

Forum Post: RE: TPS7A6550-Q1 output capacitor

David Xu1 — Mon, 17 Jun 2013 06:27:00 GMT

Hi Atsushi-san,

I am so sorry for the late reply as we had one week national holiday last week.

Our designer had get the simulation environment setted up for several days and they are doing the simulation currently. I just checked with them, the result will come out the day after tommorrow.

Best regards

David Xu

Forum Post: TPS7A66xx-Q1　Output Capacitor

Atsushi — Mon, 17 Jun 2013 04:59:00 GMT

I would like to confirm the output capacitor for TPS7A66xx-Q1.

The customer wants to use the electrolytic capacitor 330uF with the ceramic capacitor 0.1uF in parallel.

Are there any problem by the capacitors?

I think it will be stable because TPS7A66xx-Q1 has the stable region by the ESR and the capacitor (bigger than TPS7A65xx/63xx-Q1).

If possible, could you please teach the required ESR (with the capacitance).

Best regards,

Atsushi Yamauchi

Forum Post: RE: SN65HVDA100-Q1 Question about delay time

HIDE — Wed, 12 Jun 2013 10:29:00 GMT

Hi John,

Thank you for the kindly explanation.

Best Regards,

Hide

Forum Post: RE: TPS62065QDSGRQ1

Kento Harada — Mon, 03 Jun 2013 23:06:00 GMT

Ben san

Thanks!!

Kento

Forum Post: RE: Help on PGA400 Offset Correction

Martin Stein — Mon, 03 Jun 2013 21:51:00 GMT

Due to lack of activity this thread is closed for the time being.

Forum Post: RE: The solutions against battery reverse connection and minus surge for UCC27201-Q1

Mahmoud Harmouch — Fri, 31 May 2013 00:29:00 GMT

In this circuit the only path due to negative voltage is VSS, HS pin R2, upper FET body diode and the inductor. This is due to ESD diode between VSS and HS pin.

Forum Post: RE: TPIC6C596 cascade operation

David Xu1 — Wed, 29 May 2013 02:57:00 GMT

Hi Atusushi-san,

It takes 7 and a half clocks to get signal transfer from SER IN to SER OUT, then it will takes about 60 clocks for signal transfer from Device1 SER IN to Device 8 SER OUT if there are 8 cascade connections. The delay time is depended on the period of SRCK and the whole delay time=60*SRCK period.

How many cascade connections depend on how long delay time the customer can accept. Usually they do not want the delay time can be found by human eye.

In conclusion, 7 or 8 cascade connection is OK, just be care of the delay time.

Best regards

David Xu

Forum Post: RE: ISR Corruption Issue

Clancy Soehren — Tue, 28 May 2013 15:40:00 GMT

Jeremy,

Of course I understand not being able to post your code here. I was more asking if you had created a shorter test program specifically for this issue that you could share.

How would you like to proceed? Is there anything I can do on my end to help?

-Clancy

Forum Post: RE: TPS65381 - Watchdog related issue

mohamed mohideen — Sat, 25 May 2013 08:54:00 GMT

Hello Mr.Michael,

Thank you very much for your valuable comment. As we corrected the timings as per your suggestion, It is working fine.

Thank you once again.

Mohamed Mohideen

Forum Post: RE: TPIC8101 Integrator Details

Clancy Soehren — Fri, 24 May 2013 23:00:00 GMT

Garrett,

The math for the system transfer equation is worked out on pages 13-14 of the training pdf, and the math model follows the example at the end of the pdf. If you post your Simulink model, I'll take a quick look at it. The integrator doesn't do any special peak extraction, but the transfer equation is assuming a sin wave input.

-Clancy

Forum Post: RE: TPS65381-Q1 Transients

EdWalker — Fri, 24 May 2013 22:20:00 GMT

Show is the right word here.
To demonstrate how it would fail it will need to be tested on the actual PCB, subject to transients and make it fail and see what happens.
We can't predict, other that what I mentioned previously, exactly how it will fail, nor if it will fail the same way every time.

Forum Post: RE: UCC28950

Wen-Shin Wang — Wed, 22 May 2013 14:48:00 GMT

Due to lack of activity for several weeks, this post will be closed. If there are any new updates, this thread can be opened once again.

Forum Post: RE: the setting of FET ON constantly for UCC27201-Q1

Mahmoud Harmouch — Mon, 20 May 2013 19:50:00 GMT

The FETS are controlled by the driver input signals HI and LI. There is no problem as long as the these signals are complemetary. It is good to add some dead time to avoid shoot through.

Forum Post: RE: TL720M05-Q1 stability for output capacitor

David Xu1 — Fri, 17 May 2013 02:22:00 GMT

Hi Atsushi-san,

From the latest bench testing result. Please select cap according to below request: Cout>=68uF, ESR between 1ohm and 5ohm range.

Please be aware, if electricity cap is selected, their ESR would increase significantly under low temp, customer should make sure the ESR of the cap should be in 1ohm and 5ohm range under all temp.

My suggestion is that after selecting output cap, do practical bench test on bench with customer.

Best regards

David Xu

Forum Post: RE: How to stop TPS65381 resetting function?

Peter Steffan — Wed, 15 May 2013 08:44:00 GMT

Hi Jiaming,

once the watchdog function of the TPS65381 is activated you cannot stop it anymore as this is a safety feature.

Before you activate the watchdog, you could add a function in in your software, which recognizes (i.e. by checking a I/O pin),.if you want to execute application code or if you want to program the TMS570. Depending on what you want to do, the watchdog gets initialized or not.

However, in order to reprogram your TMS570 you can do the following: Power up your hardware with TMS570 held in reset so that program execution cannot start and TPS65381 does not get initialized. After 600ms the TPS65381 enters SAFE state and you can release the reset from TMS570 and reprogram the device.

Following some more ideas how to get the TMS570 reprogrammed, but they require hardware modification:

1. Prevent the TPS65381 to be initialized by i.e. open up a SPI connection

2. Prevent TMS570 to get reset by TPS65381 by opening the reset connection from TPS65381 to TMS570. Make sure the reset line on TMS570 side is pulled high.

Hope this helps!

Best Regards,

Peter

Forum Post: RE: TPS7A6550-Q1 PSpice Model

David Xu1 — Wed, 15 May 2013 01:31:00 GMT

Hi Atsushi-san,

Please send these information to my email d-xu@ti.com, let us solve this question offline. Thanks!

Best regards

David Xu

Automotive

Forum Post: RE: SN65HVDA100-Q1 Question about dominant output

Forum Post: TL720M05-Q1 Question about Input Voltage Drop

Forum Post: RE: TL720M05-Q1 Output current limit specification

Forum Post: The ultrasonic sensor for PGA450-Q1

Forum Post: RE: TPS7A6550-Q1 output capacitor

Forum Post: TPS7A66xx-Q1 Output Capacitor

Forum Post: RE: SN65HVDA100-Q1 Question about delay time

Forum Post: RE: TPS62065QDSGRQ1

Forum Post: RE: Help on PGA400 Offset Correction

Forum Post: RE: The solutions against battery reverse connection and minus surge for UCC27201-Q1

Forum Post: RE: TPIC6C596 cascade operation

Forum Post: RE: ISR Corruption Issue

Forum Post: RE: TPS65381 - Watchdog related issue

Forum Post: RE: TPIC8101 Integrator Details

Forum Post: RE: TPS65381-Q1 Transients

Forum Post: RE: UCC28950

Forum Post: RE: the setting of FET ON constantly for UCC27201-Q1

Forum Post: RE: TL720M05-Q1 stability for output capacitor

Forum Post: RE: How to stop TPS65381 resetting function?

Forum Post: RE: TPS7A6550-Q1 PSpice Model

Forum Post: TPS7A66xx-Q1　Output Capacitor