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CPU cycles on load/store a line

Cheng Wang66110
Intellectual 910 points

Hi all,

Could you please provide me the number of CPU cycles on loading and storing a line from L1, L2, MSMC and DDR respectively for DSPs on KSII?

I did measured at my side, but not quite sure what I measured is accurately enough. I am only sure that load from L1 should take only 1 CPU cycle.

Thanks

Cheng