Hi all,
Recently I am reading the DSP cache guide, SPRUGY8, and trying to turning L1 and L2 on and off. What I found if I did not specify anything on the cache control, L1D is on by default, and L2 is configured as SRAM.
I just used the routines I found from csl_cache.h, CACHE_getL1DSize(); CACHE_getL2Size(); and found that CACHE_L1_MAXIM3 = 7, and CACHE_0KCACHE = 0. Is that correct?
To enable both L1D and L2 cache, I simply used the following routines:
76 DSP_wbInv_L1D();
77 CACHE_setL1DSize(CACHE_L1_32KCACHE);
78
79 DSP_wbInv_L2();
80 CACHE_setL2Size(CACHE_512KCACHE);
81
82 CACHE_enableCaching(128);
Which essentially set L1D as 32K cache and L2 as 512K cache.
What I am not sure is the line 82:
82 CACHE_enableCaching(128);
If I turned on L1 and L2, should I really need to call this routine? It sets the 16 MB external memory from address 0x8000 0000 to 0x80FF FFFF external memory as cachable, of which 0x8000 0000 is the starting address of the DDR3 memory...
What my understand of the routine is to set a specific memory address as cacheable. However, if I set L1D and L2 as on, and I wanna the entire DDR and MSMC memory cacheable, do I really set a specific region as cacheable?
Another question: Is MSMC memory an internal or external memory? Can a data in the MSMC load through the L2, i.e., MSMC is the next lower-level memory of L2, or MSMC is in parallel with L2?
Cheng