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cachability on C6678 DSPs

Hi all,

Recently I am reading the DSP cache guide, SPRUGY8, and trying to turning L1 and L2 on and off. What I found if I did not specify anything on the cache control, L1D is on by default, and L2 is configured as SRAM.

I just used the routines I found from csl_cache.h, CACHE_getL1DSize(); CACHE_getL2Size(); and found that CACHE_L1_MAXIM3   = 7, and CACHE_0KCACHE   = 0. Is that correct?

To enable both L1D and L2 cache, I simply used the following routines:

76 DSP_wbInv_L1D();
77 CACHE_setL1DSize(CACHE_L1_32KCACHE);
78
79 DSP_wbInv_L2();
80 CACHE_setL2Size(CACHE_512KCACHE);
81
82 CACHE_enableCaching(128);

Which essentially set L1D as 32K cache and L2 as 512K cache. 

What I am not sure is the line 82: 

82 CACHE_enableCaching(128);

If I turned on L1 and L2, should I really need to call this routine? It sets the 16 MB external memory from address 0x8000 0000 to 0x80FF FFFF external memory as cachable, of which 0x8000 0000 is the starting address of the DDR3 memory... 

What my understand of the routine is to set a specific memory address as cacheable. However, if I set L1D and L2 as on, and I wanna the entire DDR and MSMC memory cacheable, do I really set a specific region as cacheable?

Another question: Is MSMC memory an internal or external memory? Can a data in the MSMC load through the L2, i.e., MSMC is the next lower-level memory of L2, or MSMC is in parallel with L2?

Cheng 

  • Even you didn't configure the cache, the default setting is applied when you power it up, or GEL file may configure the cache setting when you connect the core.

    Line 82 is set MAR128 (for the first 16MB DDR3) is cacheable. if you wanna the entire DDR and MSMC memory cacheable, you need to set those MAR registers one by one.

    Regards, Eric

  • Thanks, Eric. 

    Regarding to the MSMC, do you mean the MSMC is not cachable by default? So we couldn't not assume that MSMC is a lower-level memory of L2, right? So in order to load the data on MSMC through L2, do I need to set the MAR bit cachable for the starting address of MSMC?

    From the  SPRUGW7, I read:

    MSMC SRAM can serve as a Shared Level 2 or Level 3 memory:
    • Shared Level 2 memory—The MSMC memory is cacheable by L1D and L1P
    caches; L2 will not cache requests to MSMC SRAM.
    • Shared Level 3 memory—The MSMC memory is not directly cacheable at the L2,
    but is cacheable in L1D and L1P. However, if it is remapped to an external address
    using the address-extension capabilities in the C66x CorePac MPAX, the MSMC
    memory can be cached as a shared L3 memory both in the L1 and L2 caches. To
    achieve this, the caching must be enabled in MAR registers (using MAR.PC bit)
    for the remapped region.

    Therefore, according the paragraph above, for the MSMC configured in my liner command file:

    SHRAM:          origin = 0x0C000000 length = 0x00400000   /* 4MB Multicore shared Memmory */

    Since the starting address of SHRAM is 0x0C, I should set the CACHE_enableCaching(12) in order to enable the MSMC cachable, is that correct?

    Thanks

    Cheng

  • For yesterday's question:

    MSMC is considered as external memory, but it is cached through L2 or not is configurable. See the document corepac user guide (Literature Number: SPRUGW0C). 7.3.2.2.2 MSMC RAM Aliasing Scenarios, Table 7-2.

    ====

    SHRAM:          origin = 0x0C000000 length = 0x00400000   /* 4MB Multicore shared Memmory */

    Since the starting address of SHRAM is 0x0C, I should set the CACHE_enableCaching(12) in order to enable the MSMC cachable, is that correct?

    No, 4.3.7.2 Special MAR Registers

    MAR12 through MAR15 correspond to MSMC memory. These are read-only registers, the PC always read as 1. This makes the MSMC memory always cacheable within L1D when accessed by its primary address range.

    Regards, Eric

  • Thanks Eric,

    So do you know how to configure the MSMC at L2 cachable, i.e, cached through L2? 

    Cheng

  • MSMC memory using the native addresses will not be cached through L2. So if you want to do this, you have to use the MPAX registers (SECTION 7.3) to remap and access the memory via virtual addresses.  The virtual address was simply mapped to an area outside the DDR and MSMC native areas. The MAR registers can then used to cache of the virtual address region via L2.

  • Thanks, Eric, I will try and get you back.

    Cheng

  • Hi, 

    For a follow up question. If I wanna enable all DDR memory cacheable, is the code I used below correct?

    121 int i;
    122 for (i = 128; i < 256; i++) {
    123 CACHE_enableCaching(i);
    124 }

    The external memory starts from and with length:

    DDR3:           origin = 0x80000000 length = 0x20000000   /* 2GB CE0 and CE1 external DDR3 SDRAM */

    So the starting MAR bit is 128. Since the total number of MAR bits I need to set is 2048 MB / 16 = 128, the upper bound of the loop is 256. 

    I wanna make sure can it guarantee that all DDR memory is cachable?

    Thanks

    Cheng

  • Yes, that is correct.

    Regards, Eric

  • Hi,

    One more question. 

    If I disabled all the L1D and L2 like this:

    CACHE_setL1DSize(CACHE_L1_0KCACHE);
    assert(CACHE_getL1DSize() == 0);
     
    CACHE_setL2Size(CACHE_0KCACHE);
    assert(CACHE_getL2Size() == 0);

    Will setting the cachability of DDR take effects?

    int i;

    for (i = 128; i < 256; i++) {
        CACHE_enableCaching(i);
    }

  • DDR3 is cached through L1D and/or L2. If you disabled L1D and L2 cache, then the enabling of DDR3 cache has no effects.

    Regards, Eric