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ADS5263 14 bit mode operation
I plan on using the ADS5263 in a new design. I particularly want to make use of the internal "Clamp function" the device offers and was wondering if there is any further information available about his mode of operation? For example I do not plan to use the 16 bit front end at all so what should I do with the INXA inputs, float them, AC gnd or is it irrelevant as I will powering down the 16 bit front end to run in the lower power 14bit mode?
Any info would be greatly received.
When using the 14bit mode, you can just float the INXA pins.
Will include this info in the next datasheet rev
I'm starting into some VHDL design and I'm looking over the interface for the device and I was wondering if the it supports a 2 wire, 7x Serialization, Wordwise mode?? Going by the registers it appears you can configure it in this mode but it isn't mentioned at all in the "Output LVDS INTERFACE" section of the spec sheet?
Can you advise please.
Yes, the word-wise mode is supported with 2 wire, 7x serialization interface
I'm trying to get things up and running with the ADS5263 interfacing it with a Spartan 6 FPGA I have some questions regarding the functionality of the LVDS output interface and a few other things.......
1. Will the SYNC test pattern be outputted in the LVDS format I have setup? For example if I set up and LVDS output interface with 2 wire 8* serialisation in Word-wise mode will the test pattern output follow this? I'm not seeing this in my testing to date and I believe I am programming the registers correctly but I think I am actually getting a bit-wise output for the SYNC pattern? I can disable and re-enable the word wise register 0x28 and it has no impact on the SYNC pattern output, it does however impact on my deserialised data when I turn off the SYNC pattern and alternate the wordwise control bit.
Also does having the ADC set to 14bit mode have any impact on this, if I have the ADC set for 14 bit and I set the PAD two 0s bit of register 0x46 I assume the internals are clever to figure out that I need a 8x serialisation and not a 7x? Also if in 14 bit mode how is the SYNC data handled, if for example I set up for 7x serialisation on a 2 wire interface, what data is sent? Does the setting the SYNC bit force 16 bit mode ie 8x serialisation?
2. I want to utilize the clamp input function and run in 14 bit mode. Do I need to do anything in the registers to configure the SYNC input pin to be used with this mode of operation?
If you can get back to me with some answers it would be appreciated.
After reading your question, at the outset, I want to confirm that you are not getting confused between the SYNC test pattern & SYNC pin.
The SYNC pattern is a pattern of bits on the LVDS outputs useful for verifying the capture by the receiver. It can be enabled only using the register bit <SYNC PATTERN>
in register 0x45, bit D1.
The SYNC pin is used for
(a) synchronizing the digital filters & sync'ing the ramp test pattern and
(b) in the 14-bit mode for CCD applications, the SYNC pin is used to align the internal clamp signal with the external CCD reset phase. (shown by fig 54 of datasheet)
Additionally, the above synchronization can also be done using a separate register bit <EN SYNC> register 0x02, bit D13.
Now, to answer the other questions...
1) The SYNC test pattern does work with the LVDS format selected.
The word-wise mode is in register 0x28, as you pointed out.
D15 is the enable bit, while bits D0-D3 enable the respective bits.
The "SYNC Pattern" is actually in register 0x45, bit D1
2) Setting the ADC to 14bit serialization & also enabling PAD two zeros DOES change the serialization to 8x serialization.
3) In 14bit, 2-wire, the SYNC pattern becomes either one of "1110000" or "1111000" on each wire ( I need to confirm which one exactly).
4) The SYNC pattern is independent of the serialization - setting the SYNC pattern does not affect the serialization automatically
Thanks for the prompt reply. I do understand that there are differences between the SYNC pattern and the SYNC pin but thankyou for the clarity. I would however suggest that if what you say about the< EN SYNC> bit in register 0x02 is correct then the documentation needs revising as it suggests to me that setting this bit is required to enable the input pin but not to actually provide a means of "software sync" as you have suggested above.
Can you please confirm, for the SYNC pin to control the alignment of the internal clamp signal that I do not have to set any register bits.
I'm having trouble with the data I'm getting back but it may well have something to do with my Serdes in the FPGA, however I still would have expected to see a difference between using the SYNC test pattern in bit/byte wise (I see no means of controlling bit and byte wise in the Spec? Can you check this for me please) and word wise. If I enable the SYNC pattern I do get a result that contains the 8 1s and 8 0s but they are in the wrong order. For my testing I have setup for 14 bit ADC (reg B3 = 0x80 0x01) and reg 0x46 = 0x84 0x21 which should be 14 bit serialisation. PAD 2 0s and 2 wire 0.5 frame, I also have reg 0x28 = 0x80 0x0F for word wise control. Like I say the data seems to be coming back in the wrong order but with this setup if I then change the Wordwise reg 0x28 to 0x00 0x00 ie disabling wordwise my data remains the same. That is my reasoning for asking if the SYNC test pattern follows the LVDS output interface settings.
I'll check out my FPGA Serdes in a bit more detail to see if I can find any issues around it.
can you send me a mail at firstname.lastname@example.org?
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