We are using the DDC112 in continuous mode at 15MHz clock speed. A external capacity of 250pF is used.
Ocassionally (after random powerup) the DDC does behave not as expected:
a) The 40 output data bit do contain first the IN1 signals instead of IN2.
b) Further the expected delay between toggling the CONV signal and the response of the DCC /DVALID is rougly 140us instead of 280.2us.See picture below.
We see a potential root cause in the sartup behavior of the board. The CONV signal and DXMIT signal insert aftefacts due to some level conversion. See picture below.
Are the power-up spikes the cause for the DDC misbehavior or are the other aspects to proove?
Welcome to the forum! This part is actually being supported by the Medical/High Reliability forum, and I will transfer the post to that group. I can answer your question, however. The problem you are seeing is related to the CONV signal. The stability of this signal is very important on power up as this device does not have a Reset feature. Figure 28 and Table XI of the datasheet should be closely followed as should the information within the Power-Up Sequencing section on page 24. Noise on CONV can trigger this issue at start-up, so you might want to wait slightly longer than the prescribed values for both the time that you start the release pulse on CONV as well as the duration of the pulse.
we try to find a patch solution for our design (see previous post). - The idea is to provide power to the digital part of the DDC112 after the potential spikes on the CONV signal. We would use the following order of events:
Does this delayed power-up of the digital side allow a clean reset?
That sounds like it should work. The big priority is to make sure that the CONV is stable on power up.
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