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SN55LVDS31 - sensitivity to input over/undershoot
I have a question regarding the Sn55 and SN65 LVDS driver series components.
We have a space project where these are extensively used for transmitting data over two types of LVDS links.
On the transmitting side, the data is generated by an Actel one-time-programmable FPGA (SX-A family).
The line between the FPGA and the LVDS transmitted is very short (1 or 2 cm), and the output driver is rather strong on the FPGA (on this FPGA model, the I/O drive strength can not be controlled much).
This results in a bit over under- and over-shoot of the signal from the FGPA to the LVDS transmitter.
The short line between the FPGA and the LVDS transmitter has not passive components on it for filtering). The LVDS runs on VCC=3.4V and the clock is at 16MHz.
We probe it and see a peak of about 1ns time, with a peak value of about 1V. I.e when switching from 0 to 1, we get a peak over the"1" level, where. the highest point of the peak is at about 4.4V - which is about 1V over the 3.4 level of a static "1".
A similar downwards peak is seen when going from 1 to 0.
Adding passive components for filtering these peaks out is quite a hassle due to the constraints of space qualified processes.
So my question is:
How much of a problem are these 1ns peaks for the reliability of the LVDS component?
I see from the data sheet that the internal zener protection is set to 7V, but there is a specification regarding V(I) saying:
V(I) Input voltage range –0.5V to VCC +0.5V
We obviously break this requirement for a very short part of the clock cycle, but I have assumed it regards the static levels of 0 and 1.
Thanks you for any input!
I understand your situation.
Unfortunately, the specification for the absolute maximum rating indicates that VI must be within -0.5v to Vcc+0.5v. This is not a DC only specification.
The inputs also have ESD structures that are not included in the equivalent input schematics. The ESD structures will be stressed when exceeding the VI abs max specification.
It would be the best solution to place appropriate termination to improve signal integrity.
Thanks for the reply, Wade!
Yes, this question is the same as the ESA guys sent you.
If I understand you correctly, only the ESD protection diodes are stressed?
Those are designed to protect against N x 100V for 10-100 ns...1V for 1ns shouldn't be a big problem then?
Sorry Jonas, this is not equivalent.
ESD protection diodes are not designed for continuous stress.
It is recommended to improve signal integrity to within datasheet specifications.
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