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I am investigating the amount of change of the level of the signal line to a power supply variation in above items.
a) If in-put power supply voltage change 0.1V, how much influences does the level fluctuation of a signal line have? (For example, 10%)
b) Regarding above fluctuation of a signal line, please investigate from a viewpoint of both the X-axis (time-axis) and the Y-axis (signal level). ( For example, signal line has jitter at changing of a power supply. etc)
Thanks a lot.
Michael, the question you ask is very subjective to many variables, and in general would not be characterized for devices unless it impacted a specification.
However, I can make a few general comments that may help.
For a cmos output that drives to the VCC rail. If the output is under steady state, then a change in the VCC would generally reflect on the output one to one. A .1v drop will result in a .1v drop. This assumes that the device is well within the recommended operating conditions.
For other outputs that are not driven to rails, such as the differential outputs then this may not be true as there are other biasing circuits involved. If the device is operating under recommended operating conditions, then the output will be within specification.
If there is a specific issue that you are encountering, it would be helpful to provide schematic and scope plots of where the issue is occurring. We possibly can help determine source of the error(s).
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