From the datasheet(DAC5670-SP),there are some porblems i can not utterly understand.
1.when i use the FPGA as a data source, whether the DTCLK_P/N of the DAC5670 as the sampling clock when the DAC5670 receive the datas from the data source or not. 2.In the page 15,how much the value of the resister i should select at the terminal of IOUT_P/N .
3.In the page 15,which the mode of 1:1 balun i should select at the terminal of IOUT_P/N . Is the TC1-1- 13MA+ ok?
4.In the page 15,which the mode of balun i should select between the single-ended clock and differential clock(DACCLK_P/N),and can you recommend a chip used to generate the single-ended clock?
5.Are there evaluation board schematics about the chip of DAC5670 ?
Lei,
I am attaching the schematic of the EVM for your review.
6874.TIDAP-15521-02_SCH_Ceramic.pdf
Kang is going to reply with some information on balun and biasing.
Regards,
Wade
Please include some details on intended sample frequency and signal.
Please also be aware that the DAC5670-SP datasheet has been updated within the past several months to include more details on usage of the DLL.
A2. The termination resistor really depends on the type of interface that you would like to use. You may refer to the interface app note for current steering DAC
http://www.ti.com/lit/an/slaa399/slaa399.pdf
Also attached is a presentation that talks about the output power calculation for each of the transformer interface. The datasheet shows the 1:1 transformer coupled interface.
A3. If you are using transformer coupled interface, the transformer must have a center tab to connect to AVDD in order for the DAC output to be biased correctly. Think of the Ioutp and Ioutn as two current sources sinking the current. There has to be a power source at the center tab to provide the current.
Wade,
Thanks very much for you reply!
If my data source transmission rate is 200Mbps,should the sampling clock rate be 400Mbps for the DAC5670(DACCLK_P/N) ?
From the datasheet (DAC5670_SP), I know that "DTCLK is used as feedback clock to adjust interface timing. To accomplish this, the DAC5670 implements a delay locked loop (DLL)to help manage the timing interface from external data source" But when the sampling clock(DACCLK_P/N) rate great more than 400Mbps, it will sample a data repeatly, resulting a serious consequences. In this case,will the DLL work?
Lei
The output signals of the DAC5670 will be modulated by the chip of HMC497LP4, but the input interfaces of the HMC497LP4 are differencial. To connect the output signals (IOUT_P/N) to the input interfaces of the HMC497LP4,what should i do ? How to deal with the output signals (IOUT_P/N) of the DAC5670?
Lei, from the HMC497LP4, are you planning on using I/Q from 2 DAC5670 devices?
The DAC5670 does not have synchronization features to allow this effectively.
From prior question:
If your sample rate is 400MSPS, DACCLK=400mhz, then your data rate will be 200MBPS DDR on each data port.
You should not use the DLL for this sample rate, but should put DLL in RESTART, and use the external timing constraints based on DLYCLK.
Thanks for you reply!
1.I have some questions : Regardless of how much the rate of the data source ,once the rate of the data source is determined, the DAC5670 sample at the rate of DACCLK/2 ! The rate of the data source is determined by The data source or the DTCLKP/N and DLYCLKP/N ,which determine the speed of receiving data of DAC5670? What is the relationship between the rate of the data source and the sampling clock of the DAC5670 ?
2.I will plan to use I/Q from 2 DAC5670 devices to connect the IP/N and QP/N of the device of HMC497LP4. But i do not know how to deal with the interfaces between IOUTP/N of the device of DAC5670 and the IP/N and QP/N of the device of HMC497LP4! Can you recommend a solution?
1) The relationship is shown in the datasheet in Figure 17 (without the DLL)
The Tsetup and Thold is defined in the Recommended operating conditions table on page 9.
DTCLK is not required when the DLL is not used, as it is only an input to the phase detector to adjust the timing. With low frequencies < 1GSPS or so, the DLL is not effective due to its limited ability delay with a larger period.
2) I will have to confer with Kang, on if we have some information that will help with proper biasing to HMC497LP4.
However, I need to re-iterate that the DAC5670 does not have synchronization features to get an I and Q channel synchronized on two different DACs.
I am very grateful to you for your help.
1.I know that the DAC5670 does not have synchronization features .
2.I look forward to your good news about the HMC497LP4.
Hi Lei,
The HMC497LP4 is an IQ modulator with 1.5V common mode with 5V Vcc supply. With these two parameters, you can design a translation network as shown in section 4.1.1 of SLAA399. The use of pseudo DC network or non-pseudo DC network will depend on your end application and the output frequency range. If your frequency range does not require flat response near DC, than you may use pseudo DC network.
Attached are the excel spreadsheet calculator to calculate the network component values given the bias voltage, the full-scale current, and the impedance range. You will need to make sure that each P and N leg of the DAC5670 does not exceed the compliance voltage range of AVDD-0.5V to AVDD+0.5V. Once you have the standard resistor values, you may use the attached TI TINA Spice circuit to simulate your network along with filter values. TI TINA can be downloaded at ti.com.
Also, you may want to consider TI's TRF3703 and TRF3704 family of I/Q modulators. (http://www.ti.com/product/trf370417) They cover wider frequency ranges and offer better OIP3 performance. If you have any question, you may also post at the RF forum for answers and support.
-KH
Kang Hsia,
Hi Kang Hsia,
Thanks for your method about matching network between DAC5670 and HMC497LP4.What i need to do is only add a LPF,thanks agian！
Can i select the LPF shown below?
I have some questions to query you !
I find the matching network between DAC and modulators. The picture is followed:
What is mean of the output compliance range of a DAC ?
What i want to know is whether the output compliance range of the DAC5670 is +/-1V. Do the DAC5670 can directly connect the HMC697LP4 In accordance with the above way?
Of course, I will seriously consider the proposal provided by TI, and recommend it to the customer.
The filter design will depend on your system requirement (bandwidth, flatness, etc). You may refer to the app note below for detail
http://www.ti.com/lit/an/slwa053b/slwa053b.pdf
Figure 1 above is based on current source DACs (note the current source arrow points outwards). The DAC5670 is a current sink DAC (current arrow points inwards). The network will have to different due to different biasing requirement.
The output compliance range is the maximum range of DAC AC swing. For the DAC5670, it is AVDD+/-0.5V for each leg. Differentially, it is +/-1V. When you are designing the network, use transient response to check if each leg are still within the compliance voltage specification. The spreadsheet also tells you the range of the network given the full-scale current. For instance, the network that you have designed above has range of 2.8V to 3.8V for each leg. This is within the compliance voltage range.
Hi,
I can´t find the link to download Tina-ti 7.
I try to search inhttp://www.ti.com/tool/tina-ti.but I don't find it.
currently there is an issue with the download for Tina.
Here is a post that contains a shortcut to download the english version.
http://e2e.ti.com/support/development_tools/webench_design_center/f/234/p/203875/723557.aspx#723557
Just under the example download, there is a 7802.Tina90-TIen.exe link.