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Output Rate of ADS5263

Other Parts Discussed in Thread: ADS5263

Hi,

We are designing a board with ADS5263 data converter.

We plan to use a frequency of 12.5MHz  on the CLKP pin (input in the single ended mode).

My question is, what will be the LCLK, ADCLK and bit clock frequencies in the case of :

           - the ADS5263 is configure to work with the digital filter on

           - the filters selected for all chanells are low pass with decimation rate of 4

           - the output rate selected is Fs/4

           - the serial LVDS output interface use is 1-Wire 16xSerialization.

In the datasheet (SLAS760C) there is a case like figure 69 which shows the timings for the "normal" case (no decimation).

So what will happen if we use the configuration describes above.

Does the frame clock (ADCLK) will be Fs/4, the bit clock (LCLK) will be 2*Fs and the data rate 4*Fs?

Thanks in advance.

  • Hi,

    The LVDS output "bit" rate of the ADC is unaffected by decimation as well as the output data rate. However, the 'effective' output sample rate is affected by decimation as only 1 in N of the output samples contain information when decimating by N.   Therefore, Figure 69 of the datasheet remains the same for your configuration (the frame clock=Fs; the bit clock is 8*Fs) with the exception that the OUTPUT DATA lines will toggle data for the first 16 bits, or first sample, and then remain 0 for the next N*16 bits.  Hope this helps.

    Regards,

    Christian