Hello,
LCLK frequency should be 6x bigger than FCLK/ ADCLK when register 46 config to DDR, and 12x bigger when config to SDR. That is correct, right?
But in my tests LCLK is just 3x bigger in DDR configuration and 6x in SDR configuration.
I am using internal clock (40MHz). LCLK is about 250MHz in DDR and 500MHz in SDR config.
There is another register that I need to configure and that is giving me this CLK error?
Thank you
Danilo