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AFE5805 Clock not matching

Other Parts Discussed in Thread: AFE5805, AFE5805EVM

Hello,

LCLK frequency should be 6x bigger than FCLK/ ADCLK when register 46 config to  DDR, and 12x bigger when config to SDR. That is correct, right? 

But in my tests LCLK is just 3x bigger in DDR configuration and 6x in SDR configuration. 

I am using internal clock (40MHz). LCLK is about 250MHz in DDR and 500MHz in SDR config. 

There is another register that I need to configure and that is giving me this CLK error? 

Thank you 

Danilo

  • Hello Danilo,

    We have received your query on the AFE5805 clock and hope to have some answers back to you shortly.

  • Danilo,

    LCLK should be 6x faster than FCLK, when in DDR configuration.  That is correct.

    So, if the FCLK=ADC_CLK=40MHz and in DDR mode,  then the LCLK should be about 240MHz.

    Are you using the AFE5805 EVM?

    Chuck Smyth

  • Yes I'm using AFE5805EVM RevB.

    In DDR configuration the LCLK is 250MHz, but the ADCLK is 76,92MHz. (I want to use DDR mode)

    In SDR configuration the LCLK is 500MHz, but the ADCLK is 80MHz.

    So the problem is with with ADCLK frequency. Can I control it changing configuration registers or jumpers?

    Danilo Camara

  • Hi Danilo,

    Let's make some terminology clear:     

    ADC_CLK is the clock going into the CLKP or CLKM inputs of the AFE. This has a maximum of 50MHz.

    FCLK is a clock coming out of the device at FCLKP and FCLKM, and the frequency should be equal to the ADC_CLK input frequency.

    LCLK should be 6 x greater than FCLK or ADC_CLK, when in DDR mode.

    Can you confirm that both ADC_CLK and FCLK look like 80MHz in DDR mode?  You cannot control the FCLK frequency relative to the ADC_CLK with registers.

    Thanks,

    Chuck Smyth

  • Hi Chuck,

    Finally I find my problem's cause.

    To be able to see this waveform, I made a clock divisor for FCLK ad LCLK, and put outputs in TSW1400 CMOS connector. I connected these outputs to digital inputs of my oscilloscope, and got wrong frequencies.

    Today I tried to connect to analogical inputs and saw the correct frequency to DDR and SDR configuration, but I also saw some distortions (probably due to high frequencies combined to some wires impedance) that was causing this wrong value. 

    Thank you 

    Danilo Camara