Forcing AFE5851 Frame Clock Phase

Hello Jason

We have received your inquiry regarding the AFE5851 and hope to have some answers back to you shortly.

Hi Jason,

The variation in t_delay across one device is +/-1ns.  Then t_delay from device to device is from 3ns to 6.4ns. Assuming no input clock skew across devices, then variation across all channels should also be 3 to 6.4ns.

Then "high" side of the frame clock will be synchronous to even channels, and the "low" side to odd channels.

Fclkin is distributed three ways: to the PLL, to the ADC sampling clock and also to a clock divider used for channel muxing.  Which needs to be half of the frequency of FCLK or ADC clk.

Thanks,

Chuck Smyth

Chuck,

That matches up well with the data sheet information, but I am trying to figure out how to synchronize the frame clock phase across multiple devices.

All of the devices will receive the same phase aligned input clock.  I want all of the frame clocks to be "low" on the same input clock cycle and "high" on the next.  I need to eliminate the possibility of having some frame clocks "high" and other frame clocks "low" for a given input clock cycle.  I need this because I need all of the odd channels across multiple devices to be sampled simultaneously with the understanding that all of the even channels will be sampled simultaneously one input clock later.

Is there a way to force this phase relationship?

Do you know how the frame clock is synchronized to the channel multiplexor selection (high<->even, low<->odd)?  The diagram in the data sheet implies that the frame clock comes out of the PLL and that the channel mux selection comes from a separate divider.  I don't understand how the PLL and the mux divider can be synchronized without some connection.

Hi Jason,

Per the datasheet specs, the frame clock across multiple devices will be 'synchronized' (within a window of 6.4ns-3ns=3.4ns) so long as the input clocks to the multiple devices are very closely aligned.

Since the maximum tdelay over temperature and across devices is smaller than the minimum sampling time period, it is guaranteed that all devices will output samples from the even channels within the same frame clock and will output samples from the odd channels within the next frame clock.  Again, this all assumes that the input clocks to all devices are aligned.

Are you seeing otherwise?

Regards,

Christian

Christian,

I will use a hypothetical example with two devices to try and ask my question more clearly

Here are some properties of my example setup

• input clock to both devices = clkin
• frame clock output from device 1 = fclk_1
• frame clock output from device 2 = fclk_2
• I have the ability to power up the devices independant from the running clkin

Here are some scenarios and questions that don't seem to be answered by the datasheet.

Scenario 1.

• clkin is running with devices powered down
• I power up only device 1 during the 100th clkin cycle (an arbitrary even numbered clkin cycle)
• How long is it until fclk_1 and the corresponding bit clock start toggling?
  • The data sheet only provides a wide range of times until valid data
• Will f_clk1 be high or low during later even numbered clkin cycles?

Scenario 2.

• clkin is running with devices powered down
• I power up both devices during the 100th clkin cycle (an arbitrary even numbered clkin cycle)
• Will both fclk_1, fclk_2, and their bit clocks start toggling at the same time?
• Is there any guarantee that fclk_1 and fclk_2 will be low during the same clkin cycles?

Scenario 3.

• clkin is running with devices powered down
• I power up both devices at a random time relative to clkin
• Will both fclk_1, fclk_2, and their bit clocks start toggling at the same time?
• Is there any guarantee that fclk_1 and fclk_2 will be low during the same in_clk cycles?

Scenario 4.

• Both devices are powered up and clkin is stopped
• I start clkin
• How long is it until fclk_1, fclk_2, and the corresponding bit clocks start toggling?
• Is there any guarantee that fclk_1 and fclk_2 will be low during the same clkin cycles?

I don't see anything in the data sheet that documents a relationship between a specific input clock cycle, some other action or signal, and when the frame clock toggles from low to high.  Without documentation of a relationship like that, I don't see how one can say that all devices will output samples from the even channels within the same input clock cycle.  You said that all devices will output samples from the even channels within the same frame clock, but I don't think it is clear what that means.  Did you mean within the same input clock cycle, within the same half of a frame clock period, or something else?

Here is an examples of information in the datasheet that would answer my question

• If the input clock is started after the device is powered up (how long after?), the first (1) and subsequent odd numbered (1+2*n) rising edges will correspond to a rising edge on the frame clock output

Thanks,

Jason