AFE5808A Output Interface Setup/Hold Timing Question

Eric,

We have received your post and hope to have a response back to you soon.

Eric,

At 40MSPS and 14-x serialization, the total bit period is 1.79ns.  So setup time would range from 0.61ns min to 1.24ns maximum.  The hold time would range from 0.55ns min to 1.18ns max.  Yes, I agree the data window is 1.16ns, but the ideal case is 1.79ns.  You do have to careful of LVDS routing and length matching, but I would like to understand the DDR flip-flop number a little bit more.  Are you look at "ds182" datasheet for Kintex-7 devices?

Thanks,

Chuck

Eric,

The Kintex-7 should easily be able to match this data rate. You must ensure to set-up the timing constraints using the fitter in the compiler, but if the channels are routed to random I/Os, the fitter might find it difficult to match the Idelays. So try to route one device to one FPGA bank. Also check Frame clock to bit clock timing constraints.

Thanks,

Chuck Smyth

Hi Chuck,

Thanks for your help.  I have timing constraints in my UCF to assume 0.7 ns setup and 0.73 hold time (these are the typical values given in the AFE5808A data sheet) on the Frame Clock & 8 Data Channels in relation to the Bit Clock.  Also, all the LVDS signals from the AFE device are routed to the same FPGA I/O bank.

Perhaps the reason I am not meeting timing could be due to the implementation in my design?  Right now, the way it is designed, the LVDS Bit Clock is received by an IBUFDS -> BUFR, and the BUFR output is used as the clock input to all my DDR flip-flops.  The Frame Clock and 8 Data Channels are also received by IBUFDS -> IDELAY -> DDR FFs.  All the input buffers, IDELAYs, and DDR FFs are contained in the same IOBs as the I/O pins, so there is minimal routing delay between these components.

The Xilinx Trace report (relevant portion copy/pasted below) shows that under the various process corners, the worst case timing failures occur for setup time on Data Channel 4 and hold time on Data Channel 1.

 TIMEGRP "afeA_in_pads" OFFSET = IN 0.7 ns VALID 1.43 ns BEFORE COMP "afeAx7P" "RISING";

 Worst Case Data Window 1.518; Ideal Clock Offset To Actual Clock 0.019;  

 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 

                   |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset| 

 Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  | 

 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 

 afeAdN<0>         |    0.746(R)|      FAST  |    0.720(R)|      SLOW  |   -0.046|    0.010|       -0.028| 

 afeAdN<1>         |    0.678(R)|      FAST  |    0.755(R)|      SLOW  |    0.022|   -0.025|        0.024| 

 afeAdN<2>         |    0.683(R)|      FAST  |    0.749(R)|      SLOW  |    0.017|   -0.019|        0.018| 

 afeAdN<3>         |    0.679(R)|      FAST  |    0.753(R)|      SLOW  |    0.021|   -0.023|        0.022| 

 afeAdN<4>         |    0.763(R)|      FAST  |    0.702(R)|      SLOW  |   -0.063|    0.028|       -0.046| 

 afeAdN<5>         |    0.697(R)|      FAST  |    0.734(R)|      SLOW  |    0.003|   -0.004|        0.004| 

 afeAdN<6>         |    0.703(R)|      FAST  |    0.726(R)|      SLOW  |   -0.003|    0.004|       -0.004| 

 afeAdN<7>         |    0.702(R)|      FAST  |    0.729(R)|      SLOW  |   -0.002|    0.001|       -0.002| 

 afeAdP<0>         |    0.746(R)|      FAST  |    0.720(R)|      SLOW  |   -0.046|    0.010|       -0.028| 

 afeAdP<1>         |    0.678(R)|      FAST  |    0.755(R)|      SLOW  |    0.022|   -0.025|        0.024| 

 afeAdP<2>         |    0.683(R)|      FAST  |    0.749(R)|      SLOW  |    0.017|   -0.019|        0.018| 

 afeAdP<3>         |    0.679(R)|      FAST  |    0.753(R)|      SLOW  |    0.021|   -0.023|        0.022| 

 afeAdP<4>         |    0.763(R)|      FAST  |    0.702(R)|      SLOW  |   -0.063|    0.028|       -0.046| 

 afeAdP<5>         |    0.697(R)|      FAST  |    0.734(R)|      SLOW  |    0.003|   -0.004|        0.004| 

 afeAdP<6>         |    0.703(R)|      FAST  |    0.726(R)|      SLOW  |   -0.003|    0.004|       -0.004| 

 afeAdP<7>         |    0.702(R)|      FAST  |    0.729(R)|      SLOW  |   -0.002|    0.001|       -0.002| 

 afeAx1N           |    0.600(R)|      FAST  |    0.666(R)|      SLOW  |    0.100|    0.064|        0.018| 

 afeAx1P           |    0.600(R)|      FAST  |    0.666(R)|      SLOW  |    0.100|    0.064|        0.018| 

 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 

 Worst Case Summary|       0.763|         -  |       0.755|         -  |   -0.063|   -0.025|             | 

------------------+------------+------------+------------+------------+---------+---------+-------------+

 

Thanks,
Eric

Hi Eric,

Here is some feedback I got on your issue:

The FPGA architecture looks fine, given that the common bitclk first goes through a clock tree and then to the individual I-delay blocks.
One thing to try straight away is to use some other I/Os in the same bank for the failing circuit. Sometimes the flexible routing fabric is spent already trying to match internal delays. In particular, we can try to place all the data inputs at the FPGA as close to one another as possible.

The ideal way to meet timing would be to connect the bitclk directly to the i-delay / DDR element, but since we have a common bitclk for eight channels that have been mapped to arbitrary I/O on the FPGA, we need to do some pin-swapping manually and see if things looks better.
Unfortunately, FPGA synthesis tools do not yet have a pin assignment recommendation tool for timing closure. It needs to be done by trials before the hardware is built.

Thanks,
Chuck Smyth