Hi,
This is Ranjith Raviprakash from Whizz Systems.
We are using AFE5809 in one of our designs and we are having issues generating Testpattern in LVDS outputs. Have any one face similar issues.
We have checked the following this,
1. All the voltages to AFE5809 is stable and good.
2. CLKP_ADC is provided with 10MHz differential clock with AC coupling.
3. Output FCLK and DCLK getting generated.
4. LVDS output is stuck to sam value and no o/p getting generated when we configure th einternal register 2 bit [15:13] to generate LVDS output.
5. CLK1X and CLK16X is floating in design.
6. We were enable to change the o/p clock frequency by configuring internal registers.
The only problem is we cannot genrate any pattern out in LVDS outputs. We need some urgent help on this.
Ranjith
