DDC112 channel1 integrator A and B drifting apart

To add to the above, this only occurs in DDC range 1 (12.5pF)
range 2 (25pF) and range 7 (50+25+12.5pF) do not show this effect.

Hello Dries,

We have received your inquiry regarding the DDC112 device.
I have assigned your post to the device applications expert.
He will get back to you as soon as possible.

Dries,

Is this behavior observed on the DDC112 EVM board or on your own board? Is this same behavior seen when you put the device in test mode? Putting the DDC112 into test mode by tying TEST high will disconnect IN1 and IN2 from the external world and inject the same 13pC charge into both inputs on each CONV cycle, this would help us rule out issues coming from external sources. 

Regards,

-Adam

Hi Adam,

This behaviour is observed on our own board. But, as the drift is between side A and B of channel 1, I do not see how the board would be of influence on this effect. Please elaborate if there are layout considerations that might cause this effect.

Setting the DDC112 into test mode the following data is send by the DDC:

(Integration time for both sides 50ms +/- 10ppm, DDC in test mode, DDC set to range 1)

Format:
Ch1A, Ch2A
Ch1B, Ch2B

............, ...........
293239, 293253
288878, 288985
293246, 293261
288876, 288989
293238, 293257
288881, 288978
293241, 293267
288875, 288967
293237, 293253
288882, 288982
293246, 293250
288876, 288972
293246, 293258
288866, 288980
293234, 293255
288877, 288963
293252, 293246
288874, 288968
293239, 293259
288868, 288975
293238, 293263
288873, 288978
293251, 293254
288875, 288969
293245, 293244
288884, 288980

No drift is observed, only a difference between side A and B of both channels. I assume this is caused by the switching arrangement as described in the apllication bulletin 'The DDC112's Test Mode'?

"Due to the nature of the switching arrangement, there is a small imbalance in the charge injection between sides A and B
during test mode. This imbalance results in slightly different effective sizes for the side A and B test packets."


Could it be that some charge is transfered from the capacitor of side A to the capacitor of side B when in normal operating mode?
Causing a higher side B integration result at the expense of the side A integration result?

Regards,

Dries

Dries,

The A-side B-side difference is probably as you said caused by the charge difference or by the A/B side matching as mentioned in the datasheet. As for the layout question, do you have switching signals near the input traces that could couple in? Are you able to average side A and B to help reduce the effect in your data?

Regards,
-Adam

Hi Adam,

Thank you for you reply

Concerning the input traces and coupling:

The input traces are short and completely surrounded by a ground plane that is not used for other signals.

All switching signals are routed from the DDC112 at the far side from the input pins on the bottom of the printed circuit board:

Concerning averaging:

As we are measuring the lowest possible charge transfers, therefor our integration time is quite long.

Averaging both sides and only unsing the result will increase the response time to much.

It would be great to find the cause of this effect to try to eliminate it instead of providing filtering.

Regards,

Dries

Hi Dries,

We are asking folks internally to see if we can come up with an explanation. Will let you know as soon as we hear something...

Regards,

Edu