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ADS52J90EVM + TSW14J56EVM questions

Other Parts Discussed in Thread: ADS52J90EVM, ADS52J90

Just got a ADS52J90EVM and TSW14J56EVM.  Trying to get them running.  The High Speed Data Converter software needs active permissions to the Windows registry for something; IT guys looking into this for me, but wish this was described somewhere.

ADS52J90EVM User's Guide (SLAU632) is pretty minimal.  There is a section "Quick Test LVDS Interface", but no corresponding section for the JESD204 Interface which is the TSW14J56EVM, and in fact the TSW14J56EVM is only briefly mentioned.

Default jumper config on ADS52J90 is for external clock on J75.  There are several on-board OSC/XTALs, but no explicit instruction on how to use them.

TSW14J56EVM Technical Documents include the nice TSW14J56EVM Design Package which includes schematics and pictures of board layers. There doesn't seem to be a similar Design Package for the ADS52J90EVM?!

  • Hi Paul,
    Thanks for your post. We will return with a reply soon. Yes, we agree that the documentation lacks some detail. In the meantime, please let us know of any specific question. Also, can you please explain the software error or give a screen capture.
    Thanks,Chuck
  • The fundamental issue with the software is that it requires admin privileges to run, at least the first time.  Our IT people don't like this.  Still working with them on a solution they will approve of in their standard Windows configuration.  Other option is to use a non-standard Windows box that has admin privileges.

    Would really like to see schematics and board layers for ADS52J90EVM.  One of the reasons for getting the Eval board is to have a working design to start from.

    Especially would to see details of LMK clock section (what does LMK stand for?) and input circuitry for ADC.

    Note TSW14J56EVM has schematics and board layer available.

  • OK, I got the schematics and gerbers. IT people are supposedly taking care of the admin privilege Monday, so we should finally be able to run the software.

    My biggest question now is the external sampling clock going into J75; specifically what amplitude and whether it should be a sine or square wave?

    Would also like specifics on what to do to use the onboard 100 Mhz OSC instead.
  • IT people gave me a "run as admin" account, so can finally run the software.  Used a 1 volt p-p sine as the clock going into J75 and was able to view digitized analog input.

    So, nowhere in the docs does it say what the characteristics of the external clock should be; software GUI shows frequency only.

    GUI has a line about "Verify clock jumpers", but other than Table 1 of jumpers and what they do, docs never say exactly how to switch clock sources. Looks like one also has to run a script?

  • In ADS52J90 EVM GUI, LVDS mode has an option for 16ch, 10x, 10b. But, JESD mode only has 14b or 12b options. Want to run JESD 16ch, 10x, 10b; how can I get this option enabled?
  • Discovered .cfg files, but there isn't one for JESD 4 lanes, 16ch, 10x, 10b.  Would like to run in this config off on-board 100 MHz oscillator.

    Don't seem to be getting any replies here; any suggestions for getting my questions answered?

  • Paul,

    Due to limitations in the Altera IP, no firmware will support a JESD parameter 'F' value that is not divisible by 4. It only supports F=4,8,12,16,.....Therefore, it is impossible to do 10x with JESD with an Altera FPGA. Please contact Altera or the JESD user guide for more detail. I can't comment on Xilinx since we have less experience with them. Therefore, the closest you will get with our EVM, without making a custom transport layer in the FW, is 12x 10b, which I trust you found in the scripts directory.

    Chuck Smyth
  • J75 can be sine or square wave at +5dbm. The 100MHz crystal cannot be used as the reference clock. The default of the LMK device (LMK is just a prefix for that device family) is to work in clock distribution mode, which just a simple divider. The Altera solution that we have provided requires a clock at Fs, and a clock at 4x Fs. Therefore, even using the 10MHz or 40Mhz crystal on board is not a good option for CDM mode. If you want to run the EVM by the crystals only, I will have to send you a new configuration of the LMK, which will use the crystal to seed an internal high-frequency PLL clock that we can use. Shall I do that?
  • Chuck,

    Thanks for the very prompt and very useful reply.  We are planning to use a Xilinx, and I think their JESD core will work with F=5.  For sure I will double check this carefully.

    Yes, I did find the various .cfg scripts.

    Paul

  • Chuck,
    Thanks for the very helpful answer. Let me play with the EVM some more using the external clock on J75 since that is more flexible. If I really need to use one of the crystals I'll get back to you.
    Paul
  • If you want the LMK configuration, I will need to know your desired ADC configuration: Channel mode, Lane mode, Serz rate, sampling frequency. Whenever you are ready.
  • csmyth said:
    Therefore, the closest you will get with our EVM, without making a custom transport layer in the FW, is 12x 10b, which I trust you found in the scripts directory.

    So, I want to run the ADC at 16ch, 100 Msps, 10b. To do this on the EVM I need to use 8 lanes, 16x, 10b, correct? 4L, 12x 10b won't go this fast, correct?

    I have it working at 100 Msps, 16ch, 8L, 16x, 10b; just want to verify that I can't run this fast on 4 lanes with the EVM. I do get an error box if I try.

    This also means a 200 MHz clock into J75.

    csmyth said:
    If you want to run the EVM by the crystals only, I will have to send you a new configuration of the LMK, which will use the crystal to seed an internal high-frequency PLL clock that we can use. Shall I do that?

    If possible, I would like to run the EVM on one of the crystals at 100 Msps, 10b. This means a new .cfg and changing the jumpers? The PLL you mention is inside the LMK chip?

    One more question about the ADS52J90 JESD interface; it looks like there is no way to turn off the 8b/10b encoding? This is required by JESD204 ?

    thanks for your help,

    Paul

  • Paul,

    Please the attachment for some simple equations using 16 channel mode. From the equation below,  your lane rate with 4L,12x serz rate would be

    20*100MSPS*12/4=6Gbps. 

    This is beyond the 5G limit of the device.10x serz would result in 5Gbps, but we have discussed the issue with that. However, I encourage you to look at Figure 62 of the datasheet.  With sufficiently short trace lengths, you can achieve a stable 6.4Gbps.  Only 5G is guaranteed for long trace lengths. Also, the EVM should have no issue with 6.4G if you want to try.

    The Dual PLL is inside the LMK clock device.  we use a seed clock like the onboard 10MHz or 40MHz to lock the first PLL and then the 100MHz VCXO to lock the high frequency second PLL.  Then we divide down from the ~2Ghz PLL frequency. We can help generate if you need.

    8b/10b is inherent to JESD204. This is how we get away with an embedded clock.

    Lane Rate = 10*Fs*2*N'/L =20 *Fs *N'/L

     

    7462.TI Healthtech 16 channel AFE JESD204B Training.pdf

  • Thanks, Chuck.

    I don't think there will be a problem on our board design with Xilinx JESD204 IP using F=5, 4L, 10x serialization which is 5 Gbps as you say. I understand now why the EVM board can't do this due to the Altera JESD204 IP.

    Not sure what you are pointing me at with "figure 62 of the datasheet" which, at least on the ADS52J90 datasheet, is a block diagram of the digital processing section. Maybe you mean Section 7.11, figures 40-43 of the ADS52J90 datasheet?

    Thanks again for your answers and the useful attachment.

    Paul (Indiana University Physics Department)
  • Oops, yes that is what I meant.  As for Altera IP,  I suggest you contact Altera, but that is the information that I have received.  I would be very curious to know if Xilinx could support this.

    ug_jesd204b.pdf

  • I looked at the Altera JESD204 IP user's guide you attached; page 2-4 says it supports 1,2,4-256 octets per frame; so everything except 3.
    So, you should be able to do 10x, 10b on the EVM since that is 5 octets per frame. The unpacking would be more complicated than what is implemented currently.

    According to Xilinx PG066 which is the user's guide for their JESD204 IP, on page 32, Table 2-23 says F can be anything from 1-256 octets per frame.
  • Are you using the ADS52J90 SING_CONV_PER_OCT mode for the JESD on the EVM?
  • The 16x, 14x 10x and 8x modes should be SING_CONV_PER_OCT=1 . The 12x should not be, if you want to pack the bits efficiently. For 16x and 8x, it doesn't really matter, actually.
  • Most of the ADS52J90EVM channels are transformer-coupled.  However, there are 2 DC coupled channels; the SLAU632 user's guide says these are used in 8 channel mode. Is there some reason they won't work in 16 ch mode?

  • No reply from Chuck on this, so went ahead and tried it.  Inputs labeled CH8 on ADS52J90EVM board show up in software in Ch 15/16 (IN29) and duplicated in Ch 16/16 (IN31) which is what I expected from eval board schematic.

    But, inputs labled CH7 on ADS52J90EVM show up in software in Ch 11/16 (IN21) & Ch 12/16 (IN23); from schematic I would expect them to be in IN25 & IN27.  IN21 & IN23 are supposed to be transformer coupled inputs.

    If I plug my signal into SMA_CH21 on ADS52J90EVM board it shows up in software in Ch7/16 (IN13).

    Mistake in schematic (and board labels) or software? I guess I could map this out, but it would be nice to have this documented.

  • So, I mapped out ADS52J90EVM inputs vs where they show up in High Speed Data Converter Pro software (16 channel mode):

    SMA Software
    CH1 Ch1/16 (IN1)
    CH3 Ch2/16 (IN3)
    CH5 Ch5/16 (IN9)
    CH7 Ch6/16 (IN11)
    CH9 Ch9/16 (IN17)
    CH11 Ch10/16 (IN19)
    CH13 Ch13/16 (IN25)
    CH15 Ch14/16 (IN27)
    CH17 Ch3/16 (IN5)
    CH19 Ch4/16 (IN7)
    CH21 Ch7/16 (IN13)
    CH23 Ch8/16 (IN15)
    CH7 Ch11/16 (IN21) & Ch12/16 (IN23)
    CH8 Ch15/16 (IN29) & Ch16/16 (IN31)

    Chuck, can you confirm this is a software or firmware bug and not a hardware issue? ADS52J90 input pinout on schematic looks correct; at least it matches data sheet.