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ADS5294 synchronization pulse specification

David Bannister
Prodigy 20 points
Other Parts Discussed in Thread: ADS5294

I have some questions about the Synchronization Pulse feature in the ADS5294 ADC. We are intending use several ADS5294 ADCs in a simultaneous sampling application, including use of the built-in data decimation function. The datasheet (page 58) gives an explanation of the use of the SYNC pulse. However, I have the following questions about pulse usage:

(1) Should a single SYNC pulse be used after power-up, rather than a continuous train of SYNC pulses? (The datasheet refers to a pulse, but Figure 60 shows a continuous train of pulses.)

(2) If a train of SYNC pulses can be used, is a potential benefit of this increased robustness with respect to power-supply glitches? Are there any disadvantages to using a continuous train of SYNC pulses?

(3) Is the required SYNC pulse timing specification independent of the ADC decimation factor used?

Many thanks,

David

  • 0
    TI__Mastermind 18285 points

    David,


    I'm assigning your post to the correct applications engineer. He will be responding to you soon.

  • 0
    TI__Genius 12025 points

    Hi David,

    How are you?

    Thank you for using our ADS5294 devices.

    replying your question:

    1) When SYNC pulse is used:

    a) ADS5294 will make an internal synchronization signal

    b) this internal synchronization signal will Reset internal Clock Divider

    c) this internal Clock Divider is used for Decimation Filter.

    Single SYNC pulse should complete the purpose unless you need to change

    Decimation Filter very often (or other purpose), you may need to use Continuous SYNC pulses.

    2) When you turn off power and then turn on power, you need to re-run the SYNC pulse again.

        When the whole Clock System + Decimation Filter System are locked,

        Next (continuous) SYNC pulse may be used for your firmware (hardware) system purpose.

    3) SYNC pulse timing is very important:

        For example, assume you could be running ADS5294 with 80MSPS clock rate.

        One clock period is only tCLK=12.5ns, then tCLK/2 = 6.25ns only.

        So the SYNC must have very fast Rising Edge (assume Clock starts from 0ns),

        from low to high only allowed within -1 ns to 6.25 ns.

        So within this 7.25 ns, to finish the SYNC pulse rising edge is necessary.

        Then the Falling Edge for SYNC pulse can be >= 12.5 ns.

    Thank you for using ADS5294.

    Best regards,

    Chen

  • 0 in reply to Chen Kung
    Prodigy 20 points

    Chen,

    Thanks very much for the reply. I have a further related question: how long does it take after issuing the SYNC pulse to the ADS5294 for the decimated output data to become correctly aligned? Is this guaranteed to occur on the next data frame, irrespective of when the SYNC pulse arrives within the previous frame?

    Regards,

    David

  • 0 in reply to David Bannister
    TI__Genius 12025 points

    Hello David,

    On the data sheet page 54, it mentions for ADS5294

    when turning on Decimation Filter, the output data may take 20 clock cycle latency

    to be observed. But this timing does not include SYNC pulse.

    Please let us ask the ADS5294 device design team

    for more description for you.

    Thank you very much!

    Best regards,

    Chen