Part Number: ADS4245-EP
I am using ADS4245-EP.
I programmed ADC for both Serial DDR LVDS and Parallel Mode but in both the cases ADC sample data is same.
I am using Sampling clock of 100MHz LVPECL. At present R_C_R filter is unmounted,as It was damping the signal (was not getting enough amplitude at the ADC input).
Input termination is 100E with Bandpass filter of 60MHz, BW 10MHz
Captured data when plotted in FPGA chipscop-pro.
1) For Input 50MHz, 1Vpp - Output was Varying amplitude of Triangular wave.
2) For frequency less than 50MHz, Ex Sine 40MHz or 35MHz expected plot was Sine. But observed plot was kind of modulated op.
3) For frequencies even smaller, 20 to 35 MHz sine/square the output samples was just toggling between almost 0 to Fullscale.
I am not able to conclude the reason.
Can you help in this?
In reply to Wade VonBergen:
Schematic is attached,
I have not read registers from serial port.
There is confusion with Data Format Offset binary which is MSB and LSB bits. As it is not mentioned Clearly in Datasheet.
In reply to Amit Jagtap:
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