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Some question about TMU THS788

Other Parts Discussed in Thread: THS788

Hi Wade, 

I used two days to study the datasheet of THS788, but I still have following question. Could you help me to solve these questions?

1.How to calculate the reference clock (1.2GHz) accuracy? Could you give me an example based on user-defined MCLK assumptions.
2.Does the 18/27/34-bit value of the master counter using 2's complement format?
3.Is the maximum value (7 sec.) of the ‘Result Interface Range’ listed in 1st page calculated by the maximum range of the master counter? 
If yes, refer to the Table 22, the max time range of the course counter should be 14.31s, then, how to derive the value of interface max value?
If not, how to get the max value of the interface range?
4.Is the value of the 40-bit time stamp registers consist of 34-bit coarse delay, 6-bit interpolator output, and 16-bit calibration value?
5.Is there any typo in the paragraph of ‘Read Operation’ in page 10?
The statement is “The THS788 allows one clock cycle, (r) for the host to reverse the data-channel direction and begins driving the Hdata line on the falling edge of HCLK pulse 12.” which is not consistent to the waveform in Figure. 3 Read Operation. Should the value of ‘12’ be ‘11’?
6.When I use the  host interface for a R/W operation, what value should I set for the Hdata pin during the r0/w0 cycle?
7.Does the 40-bit time stamp registers of a certain channel have the same value as that been shifted out at the Rdata pin?
8.Are the 16-bit calibration registers in 2's complement format?
9.Is there any suggested TI clock IC for this highly accurate and low jitter(<3ps rms) master clock MCLK?
10.Should I add an off-chip pull-down 10K ohm resister at TEMP (Pin 52)?
11.Can you offer me a reference design about the time stamp processor and the THS788?

Thank you

Po Yuan

  • Hi Po,

    I'm going to try to answer all of these. Let me know if I miss any of your questions.

    1. The 1.2GHz reference clock's accuracy is dependent on the accuracy Master Clock, and as noted on page 34, what matters most is a little Jitter as possible. Out datasheet values were all calculated with a 200MHz clock with a max 3 ps rms jitter.

    2. The counter is not 2's compliment.

    3. The 34bit counter counts from 0-14s, but the results range is 2's Compliment, so for 40bit results, the value can be -7.158s to 7.158s. The counter is free running, so you will never know where on the counter your sync is starting. For any result that lasts longer than the maximum result value (7.158s in this case), you will end up with a negative result. 

    4. That is correct. This is all performed by the ALU. 

    5. Yes, this is a typo. We are currently working on updating the datasheet to update this error. During "r0" the Host releases the line so the 788 can control the line and output data. The 788 begins control on the falling edge of HCLK pulse 11. 

    6. "r0" is simply meant to signify the single clock cycle that the host has to release the line and prepare to read data. Nothing should be written during this clock cycle. "W0" is meant to represent the single clock cycle needed to allow data to be latched. Nothing needs to be written. 

    7. The timestamp register is the most recent timestamp value calculated. 

    8. I need to confirm something here before I can answer. 

    9. The clock driver we use for our bench testing is the CDCM6100X. 

    10. No resistor is necessary for the TEMP pin reading.

    11. Schematic can be found here: https://e2e.ti.com/support/applications/hirel/int-hirel/f/936/t/333861.aspx

    Please let me know if you need any more clarification.

  • Hi Matt,

    Thank you for your reply. But I still need your helps

    1. https://e2e.ti.com/support/applications/hirel/int-hirel/f/936/t/333861.aspx  this site only show me "Group Not Found"!
        Can you offer me other link for a reference design about the time stamp processor and the THS788?

    2. Please keep to confirm this question "Are the 16-bit calibration registers in 2's complement format?"

    3. How to calibrate THS788?

    Regards,

    Po Yuan

  • Hi Matt,

    Can you suggest me some low-jitter TI clock ICs which has accuracy 1 ppm?

    Thanks

    Po Yuan