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UC1846-SP: Delay remains about 400ns (in addition to the deadtime determined by the Ct)

Kishen Someshwar
Intellectual 1625 points
Part Number: UC1846-SP

Hello Team,

I have a customer who is experiencing additional 400ns of deadtime added to the duty cycle after the oscillator starts its charging cycle. The output pins do not go high until 440ns after the oscillator starts the charging cycle.  Below is detailed on what the customer is facing :

"  We’re using a push pull topology, but I tested the chip open loop by itself as well. We tested with various values. This is not the dead time as described in the datasheet. This is after the deadtime occurs and the oscillator starts to charge back up. The delay remains about 400ns (in addition to the deadtime determined by the Ct) regardless of the timing parts, after the deadtime should have ended. 

We tested on a PCB with 1nF & 6.98k; 1.3nF & 5.23k. Additionally tested with 1nF and 4.7nF on a breadboard, with a pot for Rt. The Ct is very close to the pin on the PCB. We are using NP0 caps. 

Is there any way to get any schematics or anything on this chip? We keep running into problems with the datasheet, it is full of errors and missing information. 

In the simulation reference design, this issue does not occur, the output fires as soon as the dead time is over and the charging cycle of the oscillator starts. This issue is not modeled in the sim. 

Also please let me know regarding the schematics, as I’ve said it is frustrating to keep finding new mistakes and omissions in the datasheet. Thanks for looking into it. "

I could find much information other then thinking this might have to do with the oscillator in use. Could you point us to the correct direction towards resolving this issue.

Thank you for your time.

Sincerely,

Kishen

  • 0
    TI__Expert 7445 points
    Hi Kishen,

    Acknowledging receipt of your post. I will look investigate your concerns and provide you input on it.
  • 0 in reply to Ramesh Khanna
    TI__Intellectual 1625 points
    Thank you Ramesh,

    I appreciate your help. Also can you point me to any schematics the customer can refer to that TI endorses to use with this device. The schematics in the datasheet are not working out for the customer. Is there an EVM design associated with this kit that could be shared ?

    Sincerely,

    Kishen
  • 0 in reply to Ramesh Khanna
    TI__Intellectual 1625 points
    Hello Ramesh,

    Do you have any suggestions on this issue ?

    Thanks

    Kishen
  • 0 in reply to Kishen Someshwar
    TI__Expert 7445 points
    Hi Kishen,

    Can you share the waveform from your test board. I will correspond with you via email thus you will have my email address and can share your test data. With regards to sharing schematic, it will require an NDA.
  • 0 in reply to Ramesh Khanna
    TI__Expert 7445 points
    Hi Kishen,

    Thanks for sharing the waveforms from the test board. 400nsec delay that you are seeing when the oscillator cycle is completed and when the output pulses start is normal.
    UC1846-SP datasheet under electrical characteristics on pg. 7 under current sense Amplifier section highlights delay to output of 200ns nominal and 500nsec max.
    Similarly on pg. 8 under shutdown terminal it is highlighted delay to output of 300ns (nom) and 600ns (max).

    These delay are in the same path as the OSC output pulse. This is evident from the functional block diagram on pg. 9 of datasheet. Thus 400nsec that your customer is seeing is normal and acceptable.

    As the past is an old bipolar IC thus the delays your are seeing will not be modeled in pspice . Since customer does not have an NDA thus transistor based schematic can not be shared. Besides the schematic would not provide any value without all the transistor gains and resistor/ capacitors values on it.

    Hope this addresses your concern.
  • 0 in reply to Ramesh Khanna
    TI__Intellectual 1625 points
    Hello Ramesh,

    Thank you very much for you feedback. I appreciate it.

    Sincerely,

    Kishen