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SMV320C6727B-SP: Cooling from Package Backside

don hayashigawa
Prodigy 40 points
Part Number: SMV320C6727B-SP

Have  a question on the SMV320C6727-SP  DSP.  In our case, we would prefer not to use topside cooling of the ceramic package.  Would like to propose creating a metal  pad (~.4"X.4")  with thermal vias on the PCB centered underneath the DSP.  Thermal compound would be applied to the PCB thermal pad and then the DSP attached. The leads would then be hand soldered. Pitch is tight, but the solderer is very good.  Would this be a viable approach to cooling  the DSP?  There is data for theta junction to lid. Is there any data from junction to package backside?

  • 0
    TI__Guru 62930 points
    Don,
    The Theta JC specified in the data sheet must be a typo when it says Top of Case.
    This value should represent what you are looking for. I will follow up to confirm.
    I will need to resubmit the thermal metrics. This typically takes 1-2 weeks if all data is available.
    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    Don, here are the results of the analysis.

    Result- Theta JA-High K (standard datasheet value): 16.8
    Result-Theta JC, top (standard datasheet value): 7.1
    Result-Theta JB (standard datasheet value): 9.6
    Result- Psi JT (standard datasheet value): 5
    Result- Psi JB (standard datasheet value): 9.2
    Result-Theta JC, bottom (standard datasheet value):

    2

    Modelling Assumptions:assumed 9x9 PCB thermal via connected to 1st inner plane. MIL-STD-883 for Rth-JCbottom. JESD51 for other parameters.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 40 points
    HI Wade,
    Thanks for the information. In your analysis did you assume a thermal interface material between the device backside and the PCB? Or is the cooling only through the package leads. I should mention that we are operating in a vacuum, so there is only convective cooling and no conductive cooling.

    Also, when you says 9x9 PCB themal via do you mean a 9x9 array of thermal vias ?
    Thanks,
    Don
  • 0 in reply to don hayashigawa
    TI__Guru 62930 points
    Don,
    This application note may help with understanding the metrics.
    www.ti.com/.../getliterature.tsp

    You will primarily be interested in theta jc bottom.

    I will need to confirm the spacing and size of the array of vias modeled and get back with you.

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points
    Some additional feedback from the thermal modeling team.
    --
    Assumed there is an array of 9x9 thermal via in the PCB connecting the center pad to the 1st inner plane of JEDEC 2s2p. The center pad is solder to the package body by solder (50W/mK). The via is 1.2mm pitch per JEDEC, 300u drill, 35u wall thickness.


    The above assumptions are for JEDEC parameters only. The Rth-JCbottom which is critical for this type of package was done per MIL-STD-883; there was no PCB in this test. The package is sit directly on top of a cold plate.
    --
    Regards,
    Wade