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OMAPL138B-EP: OMAPL138EZWTA3

Part Number: OMAPL138B-EP
Other Parts Discussed in Thread: OMAPL138

Hello,

I am using OMAPL138EZWTA3 device in my current project. I am getting confuse in configuring the McASP transmit clock. I am referring the OMAP L138 Manual " Literature Number: SPRUH77C

April 2013–Revised September 2016". My confusion is, Page 129 says that McASP Clock is derived from sysclk2 either from PLL0 or PPL1 controller, and in same page AUXCLK is not connected to McASP interface.

But Page 139 Shows contradictory information, in this page both reference and module clocks are connected to McASP interface and it also says that internal clock is derived from PLL0_AUXCLK clock source which is too much confusing, I believe we can also generate McASP internal clock from SYSCLK2 as well.

Could you please clarify below mention items. In our design McASP interface is being used only for communicating between two OMAP processors, not used for Audio date transmit purpose.

1. What is PLL0_AUXCLK? is it derived directly from external oscillator connected to Aux processor?

2. Since we are planning to use  PLL0_SYSCLK2 for McASP internal clock, what is the configuration we need to follow to to derive ACLKX (25MHz and our external oscillator is also 25Mhz) from PLL0  SYSCLK2?

3. is it necessary to use PLL0_AUXCLK clock for McASP communication (not using audio data).

4. what is the difference between Module clock and TX/RX Reference clock (Figure 7-7 in page 139 of OMAP manual).

Please help me to understand above clarifications.

  • Hi Ranga,

    I've forwarded this to the design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Ranga Swamy,

    Please refer to the clocking spreadsheet that we provide for this device inorder to help with visualization of the device and MCASP clocking:

    this is a very useful tool to understand device clocking and is an interactive tool that allows you to simulate the clocks based on your clock in values.

    BAsed on the PLL clocking tree, you can see that PLL0_AUXCLK is the clock that comes directly from the external oscillator or CLKIN.  MCASP clocking is very flexible and can generate clocks from internal and external clocks connected to AHCLKX.  If you purely wish to generate everything of internal clocks here is a way you can get ACLKX of 25Mhz with OSCIN of 25Mhz.

    If you don`t want to use PLL0_AUXLCK, you can connected external clock to AHCLKX as I mentioned earlier. Module clock is the one that runs the internal logic for the MCASP module while the reference clock is the one that is used to generate the bit clock or the sampling clock

    Regards,

    Rahul

  • Hi Rahul,

    Above mentioned information is really helped to understand the McASP clocking scheme. But I couldn't edit the values in interactive tool for other combinations. Could you please share the one which I can edit the clock settings. It would be nice if you can share me the interactive tools related to OMAPL138 processors which can help me to understand the schemes very well.

    Regards
    Ranga
  • I have attached the Clocking spreadsheet here so that you can download it from here:

    4118.SYS_CLK_CALC_OMAP-L138_C674X_AM18X_v1p3.xls

    Note that when you open the file, Excel will ask you to "Enable content" at the top of the spreadsheet. Then you should be able to modify the content. Note, you need to first enter OSCIN values in the PLL Structure Tab  and then go to the MCASP tab to simulate the MCASP clocking.