Other Parts Discussed in Thread: CDCM7005, CDC7005
Dear TI experts,
When I am using the chip CDCM7005MHFG‐V, I encountered following problems which I would like to get comments from you.
Description:
We send the configuration code words in the order of “WORD0‐>WORD1‐>WORD2‐>WORD3”,
the chip locks exceptional, and the PLL_LOCK signal is “low”. If we change the order of 4
configuration code words, the chip has a normal lock. We can be sure that as long as WORD0 is
not the first to be sent, then the lock is normal. This phenomenon is an individual case, because
in the other similar applications, no matter how to send the configuration code words, the lock is
normal.
Another details is,in abnormal situation,when we heated the region of Figure 1 and Figure 2 by
heat air gun,it becomes normal.
VCXO=200Mhz;PRI_REF=SEC_REF=12.5Mhz;Y*=100Mhz
Questions:
1. Has this phenomenon occurred in other applications? Is this a normal phenomenon?
2. If we sent the configuration code words in a right order, such as
“WORD1‐>WORD0‐>WORD2‐>WORD3” or “WORD1‐>WORD2‐>WORD3‐>WORD0”, does this
indicate that the chip is working property? Will there be any other problems?
The application of the chip shows below:
Figure 2 VCXO configuration
In another application, the using chip is CDCM7005RGZT, and the relationship of configuration
shows on Figure 1 and 2. By the test we found if the PD=”1”, then the value of CP_OUT should be
1.6v. Whatever, one of product’s output is 3.3v, and the PLL_LOCK signal is “low”. The chip cannot
work property no matter sending the configuration code words in any order. What could be
possibly causes it?
VCXO=200Mhz;PRI_REF=SEC_REF=100Mhz;Y*=100Mhz