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CDCM7005-SP: CDCM7005-SP software configuration issue

Part Number: CDCM7005-SP
Other Parts Discussed in Thread: CDCM7005, CDC7005

Dear TI experts,
When I am using the chip CDCM7005MHFG‐V, I encountered following problems which I would like to get comments from you.

Description:
We send the configuration code words in the order of “WORD0‐>WORD1‐>WORD2‐>WORD3”,
the chip locks exceptional, and the PLL_LOCK signal is “low”. If we change the order of 4
configuration code words, the chip has a normal lock. We can be sure that as long as WORD0 is
not the first to be sent, then the lock is normal. This phenomenon is an individual case, because
in the other similar applications, no matter how to send the configuration code words, the lock is
normal.


Another details is,in abnormal situation,when we heated the region of Figure 1 and Figure 2 by
heat air gun,it becomes normal.
VCXO=200Mhz;PRI_REF=SEC_REF=12.5Mhz;Y*=100Mhz
Questions:
1. Has this phenomenon occurred in other applications? Is this a normal phenomenon?
2. If we sent the configuration code words in a right order, such as
“WORD1‐>WORD0‐>WORD2‐>WORD3” or “WORD1‐>WORD2‐>WORD3‐>WORD0”, does this
indicate that the chip is working property? Will there be any other problems?

 

The application of the chip shows below:

Figure 2 VCXO configuration

 

In another application, the using chip is CDCM7005RGZT, and the relationship of configuration
shows on Figure 1 and 2. By the test we found if the PD=”1”, then the value of CP_OUT should be
1.6v. Whatever, one of product’s output is 3.3v, and the PLL_LOCK signal is “low”. The chip cannot
work property no matter sending the configuration code words in any order. What could be
possibly causes it?
VCXO=200Mhz;PRI_REF=SEC_REF=100Mhz;Y*=100Mhz

 

  • Hoi,
    I apologize for delay. Both of the engineers that can support this device have been out on travel.
    I should be able to provide feedback to you tomorrow.
    Thanks,
    Wade
  • Hoi,
    I am not sure what could cause the behavior you mention. I am checking with a few others to see if they have seen this before.

    However, I would like to follow up with a few questions.
    1) In the first case, if you load Word 1,2,3, 0 and get a lock. If you were to write word 0 multiple times, I expect that lock will remain?
    In order for word 0 to cause non lock, it has to be after reset, PD, or power cycle? Can you confirm.
    2) Can you confirm that SPI timing is robust? Can you provide timing captures of all the words being loaded? (CTRL_CLK, DATA, LE)
    3) Can you confirm that SPI programming is applied after reset or PD is de-asserted?
    4) Can you provide the programming of Word 0-3?

    For the second case.
    Applying PD high will enable the charge pump and device will attempt to lock. The voltage at CP_OUT will become whatever voltage is required to control the VCXO to lock the device. If frequencies or filter not appropriate, then the CP_OUT will hit its extents (0V or 3.3V depending on phase detector).

    Have you validated the feedback parameters for your VCXO and frequencies? In appropriate parameters can cause poor performance or loss of lock.

    There is a calculator for VCXO, and feedback filter located here:
    www.ti.com/.../toolssoftware
    This should be linked to the -SP folder too, but as of right now it is broken.

    The name of the software is : CDC7005 and CDCM7005 PLL Loop Bandwidth Calculator
    There are two versions, 1 labview based, and 1 excel based.
    The labview version is a little better.

    Regards,
    Wade
  • Hoi,
    Do you still have issue? If not, please reply back with your solution.
    If this resolved your issue, please click "This Resolved My Issue" on the forum.
    Thank you.
    Wade