Hi,
Do we have a timing diagram of SN54LS673 as we have for SN74LV595A as below? Customer needs a similar part as SN74LV595A, but the shift needs to be 16-bit. Is SN54LS673 a correct fit? THanks!
Antony
Hey Anthony,
We don't have an official timing diagram, but I was able to create what a 16 bit shift register would look like below. Will this work for your customer?
Hey Anthony,
As far as a reference design schematic we don't have one available, however depending on what package the customer wants we have the CAD/CAE symbols at the bottom of this page: 
Below is an exact timing diagram for the part, note that SER/Q15 may be different that what the customer is used to as the final output of the shift register and the serial input are the same pin and the function of the pin is changed using the R/nW pin.
Thanks,
Daniel
Hi Daniel,
Regarding CAD/CAE symbols you mentioned in http://www.ti.com/product/SN54LS673/pinout-quality#cadsymfoot , we only list packages as below without the one (SOIC) that customer needs.
Can you provide something like land pattern as below for this chip? Customer's rule still need chip vendor to provide this information for their internal process.
THanks!
Antony
First, to disambiguate my terminology. A clock pulse refers to a pulse that triggers the clock. In logic systems, a pulse looks like this:
(image borrowed from: https://en.wikipedia.org/wiki/Pulse_(signal_processing) )
And for the SN74HC595B, the clock is triggered by a rising edge, thus it is triggered by the low to high transition in the shown waveform.
When RCLK and SRCLK are tied together, they will trigger simultaneously, which means that whatever data was in the registers will be sent to the outputs (by RCLK) and, at the same time, the data in the registers will be shifted by one place. Here's an example to try to clarify:
For the purposes of explanation, I made a simple block diagram of a shift register with output registers, like HC595)
Loading in some random data to start (0 1 1 0) we get this:
Note that the data at the input won't be shifted in until a clock pulse happens on SRCLK, but the output at Q_D' is always the same as the data in register 'D' (the fourth register from the start). Also, the output registers are all starting at 0 in this example to show that RCLK causes the shift register data to get loaded into the output registers.
After the first simultaneous pulse on SRCLK and RCLK with everything as shown above, you get this output:
Note that the original bit pattern in the shift registers has now been loaded to the outputs (0 1 1 0), the data has been loaded into the shift register, and all shift register values have shifted by one to the right (1 0 1 1).
Now apply another pulse at SRCLK and RCLK simultaneously:
Now the serial shift registers contain 0101 and the outputs contain 1011.
If you look at this purely from the outputs QA, QB, QC, QD, the outputs are behind the inputs by a clock cycle.
i.e. If you want to load data into the shift register _and_ send it to the output registers, then you must clock the data in (4 bits = 4 clock pulses) and then send one additional clock pulse to get the data to the output (a total of 5 pulses, or N+1 with N being the number of bits loaded). For a system with 2 8-bit shift registers in series, you would need to load in 16 bits of data, then send a 17th bit to get all 16 bits to the correct outputs.
I hope this helps to clarify this a bit.
