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DAC5670-SP: Figure 12 Explanation

Richard Elmquist
Mastermind 45250 points
Part Number: DAC5670-SP

I have a customer asking the following questions about figure 12 in the data sheet:

Our application involves sending the digital inputs DA(0:13) and DB(0:13) from a digital power domain via LVDS, to the DAC, which sits in its own separate analog power domain. I am attempting to estimate potential leakage/return current to the digital domain from the DAC DA(0:13) and DB(0:13) inputs. We will connect the two domains’ GND references via high-value resistor that can accommodate the leakage current. 

The datasheet provides a model that contains fixed current sources (figure 12). Do you know what current source value should be assigned to these symbols in order to get an accurate representation of the internal circuitry?

Thanks for your help with this!

Richard Elmquist

  • 0
    TI__Guru 62930 points
    Richard,
    We will have to investigate this further. The designer for this device is no longer within TI.
    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    TI__Genius 14540 points
    Hi,

    Differential signaling is used in low signal level systems (such as LVDS) to mitigate the potential for return currents across power domains. Assuming very well matched diff pairs, the return currents on Dx_P and Dx_N will be equal and opposite and, therefore, will sum to zero. Any mismatch will result in non-zero sum of return current but this will be very small.

    Regards,
    Christian
  • 0 in reply to Christian Yots
    TI__Mastermind 45250 points

    Christian,

    Thanks for your response!

    You mentioned very small. What do you mean by this? I think that this is the crux of this question. Is this something we can define or do we just state that the mismatch will produce a very small amount of current? I think that this is why they were looking for the values of the internal current sources shown. If we cannot answer I understand. Please let me know if we can define "very small" with any greater precision.

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 45250 points

    Christian,

    Have you been able to look at the additional questions I posed?

    Can we quantify this at all? Can you describe the current sources for the customer?

    Thanks for your help with this!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Genius 14540 points
    I have posed the question to the original design team but have not received a reply yet. Assuming a transistor Beta of 100 and a mismatch of 1%, means the possible leakage current on the base of input buffer is 1/10000 of the collector current or 100nA for a hypothetical bias of 1mA. This is for each input pair. Of course, mismatch will vary positive and negative across all pairs to that the cumulative leakage current is the sum of all so predicting that current is very difficult. A worst case analysis, but highly improbable scenario, with all mismatches skewed the same, yields 100nA X 29 input pairs or 2.9uA leakage current.

    Thanks
    Christian
  • 0 in reply to Christian Yots
    TI__Mastermind 45250 points

    Christian,

    Thanks for your reply. I am sorry I did not see it. I did not receive any email that confirmed the response.

    This will be more than sufficient and I appreciate all of your help!

    Richard Elmquist