This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV3011-EP: Stabilize delay of ref output voltage after power-up at low temperatures

Part Number: TLV3011-EP
Other Parts Discussed in Thread: TINA-TI, TLV3011

Hi all,

I have a customer facing an issue with the TLV3011-EP at low temperatures at <-10°C. The REF output voltage of the comparator takes time to stabilize up to its nominal value after power-up and the duration even increases as the temperature decrease (~8s@-15°C, ~30s@-30°C).

It should not be a batch issue. The behavior is also visible when simulated in TINA-TI and only in this certain configuration.

It was observed that:

  • The issue occurs if the +15V (monitored voltage, IN -) is powered-up before the +5VA (V+ of the comparator).
  • The issue does not occur if we reduce the V+ from 5V to 3.3V. REF output stabilizes then directly with V+ without delay.
  • The issue does not occurs with the TLV3011 connected as voltage comparator IC54 (i.e. when voltage is applied first on IN+ and not IN- as with faulty circuit).

The customer tries to understand the observed behavior, and particularly why it does not appear if the V+ voltage is reduced or why it does not appear in the case where the voltage is first applied on IN+ instead of IN-.

Can you see the cause for this issue? Might any capacitance be affected by the low temperature?

Many thanks for your help.

Best,

Miriam

  • Miriam,
    The engineer that normally supports this device is out of the office. We will have a backup take a look at this and reply soon.
    Regards,
    Wade
  • Miriam,

    Unfortunately the back up for the primary support is also unavailable.

    I took a look at this in TINA trying to reproduce.  

    I was not able to reproduce an excessive delay in TINA.   The plot above is not showing delay, but a point by point DC analysis.

    I was able to simulate 15V at T0, and then a ramp on the 5V supply after slight delay.   I did have issues with convergence and had to set initial conditions to 0 to get simulation to work.

    This yielded approximately 19uS delay for VOUT to stop driving low.

    I would not expect TINA to be able to simulate the cold temp issue as described.

    I will continue to investigate any issues with cold start-up.

    Regards,

    Wade

  • Wade,

    thanks for taking care of this case. I attached a wrong picture, it's true, that is just a DC analysis.

    I don't have a description how the measurement was done in the screenshot above, unfortunately. But this might give you an insight into the case.

    I also expected TINA to have issues to simulate this.

    Can you do tests by any chance?

    Thanks and best regards,

    Miriam

  • Miriam,
    Could you supply a few more details?
    Does this occur on multiple devices? (how many?)
    Can you get description of signals in the scope shot? Is channel 4 the vref?
    It would be good to see a close up shot of what is occurring at time zero with signals. It appears there is some glitching.

    Regards,
    Wade
  • Miriam,
    I was able to obtain some additional feedback from some experts.
    Powering up the IN- or IN+ prior to V+ can cause internal nodes to get charged up and this may cause errant behavior.

    It would be recommended to power V+ prior to the comparator inputs.
    If this answers your question, please click "This Resolved My Question"
    Regards,
    Wade
  • Wade,

    many thanks for the reply.

    I got new information from the customer:

    The glitching on the previous picture was due to some improper power supply ramp-up for a specific test we made. These new pictures don’t show the glitching.

    The picture “scope_Vcc_5V” shows the results obtained for a V+ of 5V and the picture “scope_Vcc_3.3V” shows the results obtained for a V+ of 3.3V.

    They sequenced manually the power supplies to clearly see the delay between IN- and V+. In their design this delay is shorter. A few ms.

    The issue does occur on multiple devices. They confirmed that it is not a batch issue since they changed the components using a complete different batch and observing the same behavior.

    A further question is if powering up the IN- or IN+ prior to V+ cause issues even if they remain with the datasheet recommendations i.e. voltage on IN+ or IN- does not exceed V+ by more than 0.5V ?

    They use the same device in various connection schemes also powering-up IN+ or IN- before V+ and they don’t observe the issue. And they don’t observe the issue if V+ voltage is reduced to 3.3V.

    They need/want to understand what is happening internally in the device to validate any potential redesign.

    Thanks for your help and best regards,

    Miriam

  • Hi Miriam,

    As we discussed through email, if the inputs are powered up before the supply, it could bring the part up in an unstable state.  We do not have characterization data on what how big the delta needs to be before a problem occurs but it is likely to change with temperature and vary from lot to lot. 

    If there are more questions, let me know, otherwise can you mark the issue as being resolved.

    Kirby