Other Parts Discussed in Thread: ADC128S102
Hi team,
The datasheet for this part indicates that the SCK needs to run between 0.8MHz and 16MHz, which is a bit unusual for SPI interfaces. However, the datasheet appears to give a bit of wiggle room. I am interested in testing this part on an upcoming design. Test access will be via an adjacent FPGA with JTAG, so my pattern rates will be substantially lower than 0.8MHz. Is it possible to determine if the part will actually operate at a slower clock rate?
Note: I'm referencing table 6.3
Thank you.