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TLK2711-SP: TLK2711-SP Power On Reset

Ryuuichi machida
Guru 11515 points
Part Number: TLK2711-SP

Hi,

I would like you to confirm about below.

* According to datasheet, there is following figure.

  Figure 12. Power-On/Reset Timing Diagram

According to this figure, GTX_CLK should be ramp up first, and after that "ENABLE, LCKREFN" should be ramp up.

Finally, Power should be ramp up.

However, there is no description about duration b/w each signals.(Ex Period b/w "GTX_CLK and ENABLE" etc)

The question is

1. Is my understanding about required sequence which is described below correct ?

"GTX_CLK should be ramp up first, and after that "ENABLE, LCKREFN" should be ramp up. Finally, Power should be ramp up."

2. If above sequence is correct, is there any requirement about duration b/w following each signals ?

2-1. GTX_CLK to ENABLE

2-2. ENABLE to LCKREFN (I understood that this is not mandatory.)

2-3. LCKREFN to Vcc/VDDA

Thanks in advance,

  • 0
    TI__Guru 62930 points
    Ryuuichi,
    The order of the signals for the POR, are not important, the only requirement is the duration that all requirements are met.
    Regards
    Wade
  • 0 in reply to Wade Vonbergen
    Guru 11515 points
    Hello Wade-san,

    >the only requirement is the duration that all requirements are met.
    Do you mean"Min 1ms" which is described "Figure 12. Power-on/Reset Timing Diagram" of datasheet at above sentence ?

    BR,
  • 0 in reply to Ryuuichi machida
    TI__Guru 62930 points
    Correct. They all must be true at same time for 1ms. Order is not important.
    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    Guru 11515 points

    Hello Wade-san,

    Thank you for your reply.

    >Correct. They all must be true at same time for 1ms. Order is not important.

    Umm, now my customer have problem, then we suspect about power on reset sequence.

    You said that the requirement is only duration, but if so, why is the diagram on Power on reset a sequential diagram as shown below ?

    In customer's situation, they can observe device sometimes works correctly, but they can also observe device sometimes does NOT work correctly.

    (They perform loopback test.)

    It seems that the order also important from above, so could you please re-confirm whether we can ignore above order or not ?

    Thanks in advance,

  • 0 in reply to Ryuuichi machida
    TI__Guru 62930 points
    Ryuuichi,
    The labeling of 1ms was intended to show that the timing of each signal relative to each other was not relevant, and only the duration. All signals have same minimum duration. The order is not relevant.

    Can you provide more information on failure, and power sequence used?
    What kind of loopback test is being run? External, Internal, PRBS?

    If the above requirements are followed, then the failure should not be related to the correct power on sequence.
    Additionally, if device is used as receiver (as would be in loopback), then the requirements of reset will be met. The reset sequence insures that the receiver gets operated after power up to fully complete its reset.

    Regards,
    Wade
  • 0 in reply to Wade Vonbergen
    Guru 11515 points
    Wade-san,

    Thank you for your reply.
    >Can you provide more information on failure, and power sequence used?
    > What kind of loopback test is being run? External, Internal, PRBS?
    I will send detail on Email.

    BR,
  • 0 in reply to Ryuuichi machida
    TI__Guru 62930 points
    This is being addressed offline. Closing post
    Regards,
    Wade