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Compiler/OMAPL138B-EP: The difficult points of the OMAPL138 platform

Part Number: OMAPL138B-EP
Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Tool/software: TI C/C++ Compiler

On the basis of OMAPL138 platform, we want to realize 24 way sampling (four independent sampling loops, 4 independent AD, each AD acquisition UA, UB, UC, IA, IB, IC path).         

   1) chip select EMA_CS[2~5] EMIFA; one for FLASH; and the 4 AD chip, CS to four, missing one; what is the solution?          

  2) the sampling frequency of 4 AD chips is controlled by PWM; at present, only 2 PWM are known on OMAPL138, and two are missing, and there is a solution           

3) there is only one input signal EMA_WAIT for the arbitration, but how does the data ready for the data of the 4 AD chips are close at the same time, and how does the EMIFA handle it? Are there any solutions?                  

  • Hi,

    The engineer supporting this device is out of the office until April 2nd. I will attempt to find another support channel but response time might be delayed. Thanks for your understanding.

    Regards,
    Christian
  • On the basis of OMAPL138 platform, we want to realize 24 way sampling (four independent sampling loops, 4 independent AD, each AD acquisition UA, UB, UC, IA, IB, IC path).
    1) chip select EMA_CS[2~5] EMIFA; one for FLASH; and the 4 AD chip, CS to four, missing one; what is the solution?
    2) the sampling frequency of 4 AD chips is controlled by PWM; at present, only 2 PWM are known on OMAPL138, and two are missing, and there is a solution
    3) there is only one input signal EMA_WAIT for the arbitration, but how does the data ready for the data of the 4 AD chips are close at the same time, and how does the EMIFA handle it? Are there any solutions?
  • On the basis of OMAPL138 platform, we want to realize 24 way sampling (four independent sampling loops, 4 independent AD, each AD acquisition UA, UB, UC, IA, IB, IC path).
    1) chip select EMA_CS[2~5] EMIFA; one for FLASH; and the 4 AD chip, CS to four, missing one; what is the solution?
    2) the sampling frequency of 4 AD chips is controlled by PWM; at present, only 2 PWM are known on OMAPL138, and two are missing, and there is a solution
    3) there is only one input signal EMA_WAIT for the arbitration, but how does the data ready for the data of the 4 AD chips are close at the same time, and how does the EMIFA handle it? Are there any solutions?
  • Hi Garin,

    Can you share the part number of the AD you are using?

    Instead of using parallel Analog to Digital (AD) converters is it possible to use serial AD converters? OMAP-L138 has one McASP with 16 serial data pins that could receive data simultaneously.

    On the basis of OMAPL138 platform, we want to realize 24 way sampling (four independent sampling loops, 4 independent AD, each AD acquisition UA, UB, UC, IA, IB, IC path).
    1) chip select EMA_CS[2~5] EMIFA; one for FLASH; and the 4 AD chip, CS to four, missing one; what is the solution?

    Perhaps you can use a GPIO or an unused upper address bit for one of the CS

    2) the sampling frequency of 4 AD chips is controlled by PWM; at present, only 2 PWM are known on OMAPL138, and two are missing, and there is a solution

    Consider either an off-chip PWM controller or use a GPIO or Timer pin. Refer to 6.30.1 Timer Electrical Data/Timing in the OMAP-L138 datasheet.
    What is the required switching frequency?

    3) there is only one input signal EMA_WAIT for the arbitration, but how does the data ready for the data of the 4 AD chips are close at the same time, and how does the EMIFA handle it? Are there any solutions?
    I can only think of software solutions that might not run at real-time speeds. This might require FPGA.

    Hope this helps,
    Mark