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DP83848-EP: voltage source ramp rate conditions

Part Number: DP83848-EP

Hello, 

For the DP83848-EP Ethernet PHY one of my customers has the below questions:

  1. What’s the voltage source ramp rate requirement?  If the voltage (AVDD33, IOVDD33) ramps up/down in milli-seconds range, is it ok? Will the PHY oscillate as voltage ramps?

  2. There is no plan to use the JTAG pins -- what pull-up/-down resistor values do I use?

  3. As voltage source (AVDD33, IOVDD33) ramps down, what is the clock output IO’s (TX_CLK, RX_CLK) behavior like?

  • Michael, I am researching this and verifying with the commercial team. Should be able to get answers back soon.
    Regards,
    Wade
  • Michael, here are answers.

    1. What’s the voltage source ramp rate requirement?  If the voltage (AVDD33, IOVDD33) ramps up/down in milli-seconds range, is it ok? Will the PHY oscillate as voltage ramps? Wade: No specific ramp rates are defined.  However, device behavior will not be deterministic until within recommended operating conditions
    2. There is no plan to use the JTAG pins -- what pull-up/-down resistor values do I use? Wade: Input pins have internal pullups, so strictly no external biasing required.  Conservative approach would be to match these with additional weak pullups (10K to 33K range) to IOVDD33.
    3. As voltage source (AVDD33, IOVDD33) ramps down, what is the clock output IO’s (TX_CLK, RX_CLK) behavior like?Wade: Once device VCC goes below minimum operating voltage of 3V, the behavior of the device is not deterministic.  

    If there is some concern on behavior during power up, it is possible to pulldown PWR_DOWN/INT to keep device in reset during power up.  It could be enabled from serial management.  This is fairly common practice.

    It may be helpful to put device in power down before power is removed if there is concern with spurious activity during VCC power down.

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade