Hello,
For the DP83848-EP Ethernet PHY one of my customers has the below questions:
- What’s the voltage source ramp rate requirement? If the voltage (AVDD33, IOVDD33) ramps up/down in milli-seconds range, is it ok? Will the PHY oscillate as voltage ramps?
- There is no plan to use the JTAG pins -- what pull-up/-down resistor values do I use?
- As voltage source (AVDD33, IOVDD33) ramps down, what is the clock output IO’s (TX_CLK, RX_CLK) behavior like?