• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 13 subscribers
  • Views 735 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM98640QML-SP: Correct use in SH mode and bias method

PRrrr
Prodigy 215 points
Part Number: LM98640QML-SP

Hello,

I am considering the use of the LM98640 to connect to a sensor providing several sets of two seperate output lines, one for the REFERENCE level and one for the SIGNAL level. Both signals are presented at the output interface at the same time. Those signals are typically swinging between 1V and 3V.

The datasheet says that the LM98640 is typically used AC coupled but I am afraid that is my case we will lose some information as the REFERENCE signal might not fluctuate much and the SIGNAL might also be slowly changing over a frame. Thus what is left would be a DC coupling of the inputs and the datasheet is giving a CDS mode example in §8.2 but no SH mode example are presented. Am I correct or am I forgetting some essential details here?

My first problem is how to bias correctly if necessary. Figure 17 in §7.3.2 Input Bias and Clamping seems to be indicating that the CLAMP internal signal or the CLPIN extarnal signal will allow to connect the OSx- to the internal VCLP and therefore force a voltage at the OSx- pin. In case of a DC coupling, this means the VCLP voltage will be applied to the sensor output and I doubt it would be a good idea.

Therefore what would be the best solution in term of range and bias?

Regards.

  • 0
    TI__Genius 14540 points
    Hi,

    I am looking into your questions and will get back to you by the end of the week.

    Thanks,
    Christian
  • 0 in reply to Christian Yots
    TI__Genius 14540 points
    Hi Again,

    It sounds like you can do a simple pseudo differential measurement by running the part in S/H mode, DC couple the inputs,and as long as the black level is below 3V, it should be OK. We don't recommend using VCLP or clamping and both should be disabled them.

    Thanks
    Christian
  • 0 in reply to Christian Yots
    Prodigy 215 points

    Hello,

    thank you for your answer.

    I am concerned about the min and max input voltages for each OSx pins since the datasheet only specifies a peak-to-peak value. Nowhere are specified some absolute values, which perhaps explain the part of the answer where you say "as long as the black level is below 3V"?

    So besides the fact that the OSx+ voltage level should always be above the OSx- voltage level (as I saw in one of the posts), is there some absolute input voltage limitations besides the obvious VDD33 and VSS33?

    Regards.

  • 0 in reply to PRrrr
    TI__Genius 14540 points
    Hi Again,

    Input range to the device (Osx+/-) is theoretically rail to rail but it is nonlinear near the rails so it is best to keep the inputs off the rails by 0.3 V. ADC full range is 2V but device absolute input range is ~0.3 V to ~3.0V, allowing for 2.7V differential since this can be gained down using the PGA. We have added this to our queue to update the datasheet so it is more clear.

    Thanks
    Christian