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SN54LS193: SN54LS193

Part Number: SN54LS193

Hello 

Iam using SN54LS193 used in the down converter mode and with input word 1 1 1 1 at A B C B input pin's with clock of 200kHz input.

Could you please suggest how can we calculate the pulse width( time taken to down convert to 0 0 0 0 from 1 1 1 1 input)and for application as the data loaded in the counter it starts down counting with down counting clock signal, at the end of down count it generated a barrow signal which resets the flip flop in the circuit.  

Also suggest what will be the input word loaded to generate the pulse width of 8usec and 16usec.

Regards,

RVP

  • Varaprasad,
    Using 200khz as your input count down clock, you will only have resolution of 5us for timing.
    Well really it is more complicated than that. You will also have to add the delay from rising edge to falling on the down counter. The falling edge of the down count triggers the output to the borrow signal.
    So, what you will have is something like this for 200kHz assuming 50% duty cycle. 1/2 period is 2.5us for the delay from rise to fall on down count.
    BCD count value Delay to borrow
    0 2.5
    1 7.5 (5+2.5)
    2 12.5 (2 x 5 + 2.5)
    3 17.5 (3 x 5 + 2.5)
    4 22.5 ...
    5 27.5
    6 32.5
    7 37.5
    8 42.5
    9 47.5

    To get closer to 8 and 16us, you will need to change the count frequency, or use a pulse down count input of at least 25ns. This will decrease the 1/2 period to be the delay from rising edge to falling edge for down count.

    You will also need to consider the starting position for down count. For example I don't believe loading 0 and down counting will initiate a borrow unless down is high when loaded with 0.

    If this answers your question, please click "Verify it as the answer"
    Regards,
    Wade
  • Hello Wade,

    Thanks for your suggestions..

    if we need to get 8usec delay with 500kHz and 16usec delay with 250kHz,what will be the down count input data to be loaded ?

    How the duty cycle of the clock will impact the BCD count delay?

    Regards,

    RVP

  • Hello,

    Could you please give your suggestions ?

    Regards,

    Varaprasad.R

  • Varaprasad,

    If your down count signal is 50% duty cycle, then you can use the table I have for the first reply, just adjust the period and 1/2 period to the new values.

    For 500Khz, the period is 2us, and 1 for 1/2 period.  

    This would adjust the table as follows for 500Khz:

    500Khz 2uS period
    count delay Borrow Total
    0 0 1 1
    1 2 1 3
    2 4 1 5
    3 6 1 7
    4 8 1 9
    5 10 1 11
    6 12 1 13
    7 14 1 15
    8 16 1 17
    9 18 1 19

    For 250khz:

    250kHz 4uS period
    count delay Borrow Total
    0 0 2 2
    1 4 2 6
    2 8 2 10
    3 12 2 14
    4 16 2 18
    5 20 2 22
    6 24 2 26
    7 28 2 30
    8 32 2 34
    9 36 2 38

    Neither case allows for 8 or 16uS delay.

    If the duty cycle can be changed to a minimum pulse, then you can substitute the width of the pulse into the borrow column above to get the new delays.  Best case, you need a 25ns pulse width.   So, the result would be the delay column plus the 25ns.

    Regards,

    Wade