Part Number: ADC32RF80
The sampling rate appears to be fixed at 2949.12 MSPS.
Is it possible to change the sampling rate?
If so, how do I change it?Which part of the data sheet should I look at?
What does offset correct mean?
In reply to Daniel Brock36:
I will wish you happy new year. ^^
While using ADC32RF80EVM, I have the following questions.
It was a question about RF frequency according to NCO setting.
Below is a summary of the actual RF frequency calculated by the NCO settings.
NCO set Wanted frequency RF frequency Offset
D908 2500.2MHz 2500.2MHz 0Hz
D906 2500.1MHz 2500.11MHz 10KHz
Q: Can I set the RF frequency in units of 100 KHz without offset in the ADC32RF80?
I want to use 2500.1, 2500.2, 2500.3MHz....
Sample clock: 2949.12MHz.
In reply to Taemin Ahn:
Happy New Year to you, as well!
I'm not certain as to what you mean by "without offset in the ADC32RF80?". Are you referring to the offset correction? If so, yes, you can adjust the NCO in 100 kHz steps with no offset correction.
The NCO can increment in 50 kHz steps, so using the frequencies (2500.1 , 2500.2, etc...) will work ok.
If you refer to the photo attached to me, put D906 and I will get 2500.11MHz.
Conversely, if you enter 2500.1MHz for frequency, D906 is output.
There is a difference between 2500.11MHz and 10KHz. I hope to get 2500.1MHz exactly.
If you have a way, please let me know what is the correct way to make 2500.1MHz.
Since the clock rate (Fs) we are using here is 2949.12 MHz, and the resolution of the NCO is 16 bits, the NCO can only move in approximately 50 kHz steps. 2949.12 MHz/65535 = 45 kHz.
From the datasheet (pg 46, 126.96.36.199), we can see that, if Fs is lowered, the NCO step size will decrease. In order to get the NCO to have a 10kHz step size, Fs must be set to 655.35 MHz. 65535*10kHz = 655.35 MHz.
You can also test this assumption in the GUI in order to see that the NCO register bits do change when making a 10 kHz increment.
Unfortunately, this does not solve your immediate issue since the lower Fs doesn't allow for an NCO output above 655.35 MHz, so I do not see a way to achieve the 10 kHz NCO step at 2500 MHz.
Thank you for your dedicated help.
I was wondering about this, but my customers want 2500.1MHz to be accurate.
I will look for other ways.
If you have any other chip solution, please ask for it.
Thanks again for your help.
One other solution I can offer would be using an ADC that has a finer resolution NCO. The ADC12DJ3200 is a dual channel, 3.2 GHz clock ADC with a 32-bit NCO, to name a few features. Taking a look at the image below, with the Fs clock set to 2949.12 MHz (as we had used before), the NCO steps in roughly 0.7 Hz increments.
Hope that helps.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.