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AFE5818 - LVDS 2x Data Rate Syncronization

Other Parts Discussed in Thread: AFE5818, AFE58JD18

Greetings.

We are using the LVDS lines in the 2x Data Rate mode in the AFE5818. In this mode, there are two channels interleaved on one LVDS line. We are having challenges in the de-serialization process....ie. sometimes, we get the two channels backwards.

We are using the Xilinx 7Z020 on an AVNET Microzed board using Vivado and it's built in Select I/O Wizard blocks

I am feeding the bit clock into a PLL and regenerating the bit clock, 1x frame clock, and 2x frame clock. I feed the frame clock into an ISERDES as data and clock it from the regenerated bit clock and the generated 2x frame clock (clk_div). My bit slip module pattern matches the frame clock as '11111111111111' by bitslipping the ISERDES. I then split the channel ISERDES output using data fifos clock on opposite edges to separate the channels.

This method works fine for the 1x data rate mode, but not the 2x mode. I think the issue stems from the fact there are '2'  "2x frame clock cycles" in one true frame clock and I can't differentiate which one is being locked onto. I might need to slip it greater than half a 1x cycle to match it, and then the channel results are backwards.

Try as I might, I can't find ANY information on how to handle the 2x data rate mode for these chips other than the datasheet. 

Are there any IP blocks that TI provides to interface the LVDS lines into a FPGA? If not.....Help!

  • Craig,

    I'm assigning your post to the correct applications engineer. He should respond soon.
  • Thanks Amy.

    Any idea on when I can expect contact?

  • Hi Craig, Please let me look into this closer tomorrow. We have some unofficial sample code, and we have some good app notes for LVDS capture, but not 2x. In the meantime, please try to provide a trigger signal at the TX_Trig SMA or LVDS connector and see if this does not sync the channel order. I will try the same.

    Thanks,
    Chuck Smyth
  • Sorry for the delay, Chuck. Been swamped.

    I will try to the TX_Trig, but it may take a bit of time!

    Craig

  • I attempted to detect which channel is what (1=1, or 1=2) by using test patterns on the AFE5818 chip. This works except that the test pattern out of the AFE5818 is not usable for me. If I set a test pattern of "sync" I get the same pattern for each channel. If I set it for "toggle" I get a nice signal that I can capture as its high for ch1 and low for ch2. HOWEVER sometimes after powerup, I get an inverted pattern, which doesn't help me at all!  I can't get a pattern that I can use. For the most part, The LVDS line pattern follows what I set ch2 to, and ignores ch1 test pattern setting

    I tried the TX_TRIG you mentioned, but I still get an unreliable (toggle) test pattern.

    Craig

  • OK. I have made some success. I ended up increasing the AFE5818 chip to 12MHz (minimum i/p for clock wizard) from 6MHz. I then feed the frame clock into the PPL and generate the clocks and div_clk for the selectIO wizard from that. Now I get consistent channel determination! I had to run the frame clock through an IBUF_DS block and then fan out to the clock wizard as well as the selectIO. I have the SelectIO set as single ended LVCMOS12. I hope that's alright.

  • Sir,
    How to synchronize the TSW1400 and AFE5818 with the continuous capturing data? that is, i need to control the AFE5818 at a trigger time only i need to capture at tsw1400. Is it possible?
  • Tom,

    If your device is the AFE5818 and not the AFE58JD18, then you don't need to control the AFE itself with a trigger. You might, however, wan't to synchronize your AFE input signal to the data capture. This can be done with the trigger options in HSDCPro. HSDCPro also has the continuous capture mode. Unfortunately, at this time, they cannot work at the same time. This has been requested and will be put into the software, but this is probably months away.

    Thanks,

    Chuck Smyth
  • Hi Chuck

    I'm using an AFE5818 and it's not so clear to me what TX_TRIG does?

        - Besides for LVDS test patter synchronization and Auto_Channel_offset_removal, can it be used to tell the AFE when to make a sample (i.e: AFE5818 only sample ADC-inputs and transmit the data when it is triggered by TX_TRIG ) ? Since in our application we need to know when data comes at ADC-inputs.

    Thanks,

    Bien

  • Bien,

    In the AFE58JD18, the TX_Trig can serve additional functions, but in the AFE5818 it is only the functions that you mentioned.  The pattern sync is very useful to debug and initialize your FPGA LVDS input blocks.  The AFE is continuously converting and continuously streaming out the LVDS, so there is no such thing as a triggered conversion.  The only exception is a temporary power-down, such as the LVDS PDN registers.

    Thanks,

    Chuck SMyth

  • Hi Chuck,
    Thanks for the verification about TX_Trig.

    Best regards.
    Bien