Greetings.
We are using the LVDS lines in the 2x Data Rate mode in the AFE5818. In this mode, there are two channels interleaved on one LVDS line. We are having challenges in the de-serialization process....ie. sometimes, we get the two channels backwards.
We are using the Xilinx 7Z020 on an AVNET Microzed board using Vivado and it's built in Select I/O Wizard blocks
I am feeding the bit clock into a PLL and regenerating the bit clock, 1x frame clock, and 2x frame clock. I feed the frame clock into an ISERDES as data and clock it from the regenerated bit clock and the generated 2x frame clock (clk_div). My bit slip module pattern matches the frame clock as '11111111111111' by bitslipping the ISERDES. I then split the channel ISERDES output using data fifos clock on opposite edges to separate the channels.
This method works fine for the 1x data rate mode, but not the 2x mode. I think the issue stems from the fact there are '2' "2x frame clock cycles" in one true frame clock and I can't differentiate which one is being locked onto. I might need to slip it greater than half a 1x cycle to match it, and then the channel results are backwards.
Try as I might, I can't find ANY information on how to handle the 2x data rate mode for these chips other than the datasheet.
Are there any IP blocks that TI provides to interface the LVDS lines into a FPGA? If not.....Help!