ADS52J90EVM: About ADS52J90 GUI

Hi Tsuyoshi,

The HMC-DAQ GUI can be run as a stand-alone GUI and be used to configure the ADS52J90 to continuously output a ramp test pattern without HSDC Pro and the TSW14xx's FPGA.

Sincerely,

Olu

Hi Olu_san,

  Thank you very much for your reply.
  Please let me ask you a additional question.

  I installed HMC-DAQ by using HMC-DAQ_GUI_INSTALLER_v2.8.exe,
  then I executed HMC-DAQ.
  However the HMC-DAQ did not run correctly with a following error message.

error_message.xlsx

  Are there any other programs that I should install?

  Would you be able to lend your expertise?


Best regards.
Tsuyoshi Tokumoto

Hi Olu-san,

  Thank you very much for your reply.

  As you said, when I started up the HMC-DAQ GUI with connecting
  the ADS52J90EVM to my PC, it ran correctly without error message.

  Thanks again!

Best regards.
Tsuyoshi Tokumoto

Hi Olu-san,

  I tried to evaluate communication between a ADS52J90EVM and
  a TSW14J56(Rev.B or Rev.D) by using Ramp Test Pattern with
  HMC-DAQ V2.8 and HSDC Pro V4.10, but it has not communicated
  correctly yet.

  As any setting is acceptable, could you please tell me how to
  communicate correctly by using Ramp Test Pattern?
    -Jumper pin setting
    -Clock frequency
    -Procedure

  Please lend me your expertise again!

Best regards.
Tsuyoshi Tokumoto

Hi Tsuyoshi-san,

What is the amplitude and frequency of the external clock signal you are providing to the ADS52J90?

What exactly is the problem you are seeing--can you describe it in more detail? Did you follow the exact steps as detailed in the EVM's user guide?

The jumper settings as specified in the user guide should help you capture a ramp test pattern in four-lane JESD mode.

Sincerely,

Olu

Hi Olu-san,

  I apologize to you for the lack of information.
  I describe the evaluation situation as follows.

1）Evaluation board setup
        ADS52J90EVM + TSW14J56(Rev.B or Rev.D)

2）Target spec
　 　JESD204B、5Gbps、16ch、16x、14bit、4Lane, 62.5MSPS
　　
3)Jumper pin setting
        Please refer to the attached file.

Reference material.xlsx
4)Input conditions
        LMK_CLKIN1(J75):125MHz,6dBm
　　Used config file:
             HMC-DAQ GUI/Scripts/ADS52J90/QUICK_START/
             ADS52J90_16ch_SINE_4L_16x_14b_GBLCLKDIV1_FSDIV4_SYSREFDIV24_20x.cfg

5)Evaluation result
       When I changed the setting value in the config file as follows
       with ADS52J90EVM+TSW14J56(Rev.D), it was able to communicate correctly
       by Ramp Test Pattern a few times.
       However, it is not able to communicate correctly now.
            *Please refer to attached file(Reference material) for error message.
　　　
　　　　・Address 0x108
　　　　　　　0x4⇒0x2
　　　　・Address 0x13B
　　　　　　　0x18⇒0xC

　　　　　FPGA CLK：125MHz
　　　　　FPGA SYSREF：10.417MHz
　　　　　ADC CLK：62.5MHz
　　　　　ADC SYSREF：10.417MHz
　　　　　　　　　
6)Questions
　　Since 0 is written at address 0x73(ADS52J90) of the config file,
        ADS52J90 is set to subclass1 of JESD204B.
　　On the other hand, since 0xF1 is written at address 0x10E(LMK04826)
        of the config file, ADC_SYSREF is not output from LMK04826.

        Is that setting correct?

       In addition, I evaluated the communication by changing the value of address
       0x10E to 0xF0 just in case, but it was not able to communicate correctly.

       If you have a config file for 5Gbps,could you please share it with me?

Best regards.
Tsuyoshi Tokumoto

Hi Olu-san,

  TSW14J56(Rev.D) may be broken.
  I will try to re-evaluate the communication by using another TSW14J56 board.

Best regards.
Tsuyoshi Tokumoto

Hi Olu-san,

  I evaluated the communication between a ADS52J90EVM and
  a TSW14J56(Rev.B),but an error appeared and
  it was not able to capture the JESD204B data.
   *I had not another TSW14J56(Rev.D).

  When the capture board was TSW14J56(RevD), no such error appeared.

  Used GUI:
     HMC-DAQ V2.8 and HSDC Pro V4.10
     HMC-DAQ V2.8 and HSDC Pro V4.5
      *I evaluated the communication by the above 2 patterns.

  Please refer to the attached file for the procedure I evaluated
  and the displayed error.

error2.xlsx

 Could you please give me some advice about this issue?
 If there is something that I should do, please let me know.

Best regards.
Tsuyoshi Tokumoto

Hi Olu-san,

  Thank you very much for your reply.
  I understand that.

  Please let me ask you a additional question.

  According to the HMC-DAQ GUI/Scripts/ADS52J90/QUICK_START
  /ADS52J90_16ch_SINE_4L_16x_14b_GBLCLKDIV1_FSDIV4_SYSREFDIV24_20x.cfg,
  0x00 is written at address 0x73(ADS52J90),and 0xF1 is written at
  address 0x10E(LMK04826).

  Hence, the ADS52J90 is set to subclass1 of JESD204B, and the ADC_SYSREF
  signal is not output from LMK04826.

  Is the ADC_SYSREF signal unnecessary?
  Is that setting correct?

Best regards.
Tsuyoshi Tokumoto

Hi Olu-san,

  Could you please reply regarding this matter?

Best regards.
Tsuyoshi Tokumoto

Tokumoto-san,

The Arria 10 should work fine, but the maximum data rate of the ADS52J90 is 6.4Gbps, for each lane. The ADS52J90 EVM ships with the TSW14J56 EVM FPGA capture card ( which uses the High Speed Data Converter Pro software). However,  the ADS EVM can communicate with a third party EVM like the Arria.  The ADS EVM will use the HMC-DAQ GUI and does not require any other software or hardware to create a ramp test pattern.

Thanks,

Chuck Smyth

Smyth-san,

  Thank you very much for your reply.

  Please let me ask you a additional question about
  configuration file for ADS52J90EVM.

  According to the HMC-DAQ GUI/Scripts/ADS52J90/QUICK_START/
  ADS52J90_16ch_SINE_4L_16x_14b_GBLCLKDIV1_FSDIV4_SYSREFDIV24_20x.cfg,
  0x00 is written to Register 115(ADS52J90),and 0xF1 is written to
  Register 0x10E(LMK04826).

  Hence, the ADS52J90 is set to subclass1 of JESD204B, and the ADC_SYSREF
  signal is not output from LMK04826.

  Is the ADC_SYSREF signal unnecessary?
  Do I need to change the contents of the configuration file?

Best regards.
Tsuyoshi Tokumoto