ADS52J90EVM: How to change the register value of 0x173 with GUI software

Part Number: ADS52J90EVM

Hello support team,

Our customer is now evaluating using ADS52J90EVM.
The register 0x173 of LMK04826 can not be written with the GUI software of ADS52J90EVM.

I have two questions.

1. What is the POR DEFAULT value of register 0x173 of LMK 04826?
2. How can I change the register value of 0x173 in the GUI of ADS52J90EVM?

Best regards,
M. Tachibana

  • Hi Masanori-san,

    In order to set the LMK register value for the ADS52J90 EVM, modify the appropriate quick startup script at C:\Program Files (x86)\Texas Instruments\HMC-DAQ GUI\Scripts\ADS52J90\QUICK_START\. 

    You can add another line for register 0x173 to the appropriate configuration file and the value you want written into it.

    Sincerely,

    Olu

  • In reply to Olu Sodipe:

    Hello Olu-san,

    The customer have already added the description of 0x173 to the config file in the following folder and try to set the register of 0x173 with starting up the GUI software.
    However, an error message appears and the all register data including 0x173 can not be loaded at all.
    C: \ Program Files (x86) \ Texas Instruments \ HMC - DAQ GUI \ Scripts \ ADS52J90 \ QUICK_START \

    I will ask you three questions again. And could you please answer all the questions.
    1. Please teach me the POR (Power On Reset) value of 0x173.
    Currently it seems that PLL 2 of LMK 04826 is not working.
    2. Why can't I write the register data of 0x173 by the GUI software config file?
    3. Is there a way to write to 0x173 by another means?

    Since it seems that PLL 2 of LMK04826 is not working, so customers are in trouble.

    Best regards,
    M. Tachibana
  • In reply to Masanori Tachibana:

    Hi Masanori-san,

    You are right--the 0x173 register is not mapped to the HMC-DAQ GUI and cannot be configured with it. But it shouldn't matter because PLL2 is not powered down at startup anyways.

    The LMK04826 on the ADS52J90EVM board is setup in bypass/division mode so its configuration files do not use its PLLs by default.
    In order to use the its PLLs, connect jumper JP4 to power the LMK04826's onboard external VCO for PLL1 then provide a clock to the LMK (either externally through J75 or via any of the onboard crystals).

    As an example, I used a 200MHz external clock on J75 with the following registers changed in the appropriate script from the scripts' folder I mentioned earlier;
    0x120 changed to 0x0A
    0x126 changed to 0xF1
    0x138 changed to 0x00
    0x147 changed to 0x18
    0x15A changed to 0x05
    0x168 changed to 0x05

    And that should generate a 200MHz signal on TP21 on the EVM.
    You should also see the D3 and D4 LEDs light up on the ADS52J90 EVM signifying PLL1 and PLL2 lock showing PLL2 is not powered down.

    Sincerely,
    Olu

  • In reply to Olu Sodipe:

    Hello Olu-san,

    I'm sorry for the late reply.
    Our customer has confirmed that PLL2 worked with the register settings you teach me.
    Thank you.

    The customer expects to output 125 MHz of signals to ADC_SYSREF and FPGA_SYSREF using the crystal oscillator (40 MHz) on ADS52J90EVM.
    The customer tried to change the register settings from yours so that the desired output can be obtained.
    However, PLL2 does not work and these clocks are not be appeared.

    Are there any register settings you recommend?
    Could you please advise me.

    Best regards,
    M. Tachibana
  • In reply to Masanori Tachibana:

    Hi Masanori-san,

    After initializing the device, modify the following register settings;
    0x10E to 0xF0
    0x138 to 0x00
    0x13B to 0x10
    0x146 to 0x10
    0x147 to 0x18
    0x156 to 0x04
    0x15A to 0x0A
    0x161 to 0x0A
    0x168 to 0x31

    With a 40MHz input clock to the LMK (either with the crystal or an external clock signal and corresponding jumper settings), that should get your PLLs in lock plus a 125MHz SYSREF.

    Sincerely,
    Olu
  • In reply to Olu Sodipe:

    Hello Olu-san,

    I'm sorry to late reply.
    Using the setting you taught, our customer confirmed the 125 MHz of SYSREF output signal.

    Based on that register setting, the customer is studying the settings of the desired operation by the ADS52J90EVM GUI software, but it does not work well.

    Could you advise us the recommended register settings which works under the following conditions in your evaluation environment?
    And would you please send us the config file of that GUI software? (Regarding ADS52J90 and LMK04826)

    I am sorry for troubling you, and I need your help.

    ----------------------------------------------------------------------------------------------
    Mode 1
    [ADS52J90]
      JESD204B Sub Class 1
          L = 4
          F = 6
          N = 12
          N '= 12
          K = 4
      Signal: Test Pattern (Ramp)
      Output rate = 4.32 Gbps
    [LMK 04826]
      Input:
          CLKin 1 = 40 MHz (using an oscillator on the board)
      Output: 
          DCLKOUT 0 (FPGA_CLK) = 72 MHz
          DCLKOUT 2 (ADC_CLK) = 72 MHz
          SDCLKOUT 1 (FPGA_SYSREF) = 7.2 MHz
          SDCLKOUT 3 (ADC_SYSREF) = 7.2 MHz
    ----------------------------------------------------------------------------------------------
    Mode 2
    [ADS52J90]
      JESD204B Sub Class 1
          L = 4
          F = 6
          N = 10 (tail bit :2bit)
          N '= 12
          K = 4
      Signal: Test Pattern (Ramp)
      Output rate = 6.12 Gbps
    [LMK 04826]
      Input:
          CLKin 1 = 40 MHz (using an oscillator on the board)
      Output:
          DCLKOUT 0 (FPGA_CLK) = 102 MHz
          DCLKOUT 2 (ADC_CLK) = 102 MHz
          SDCLKOUT 1 (FPGA_SYSREF) = 10.2 MHz
          SDCLKOUT 3 (ADC_SYSREF) = 10.2 MHz

    ----------------------------------------------------------------------------------------------

    Best regards,
    M. Tachibana

  • In reply to Masanori Tachibana:

    Hi Masanori-san,

    The TSW14J56revD FPGA's GTXCLK has to be 3X times the ADC_CLK for F=6. This is because considering 8b/10b encoding, you are looking at a data rate of 60*ADC_CLK.
    Combining this with the fact that the data rate is 20X GTX_CLK, you get the 3X requirement. You would have to configure your LMK dividers to meet this.

    You can also find the ADS52J90 settings for your configurations inside this folder on your PC (pick the right script);

    C:\Program Files (x86)\Texas Instruments\HMC-DAQ GUI\Scripts\ADS52J90\JESD\TSW14J56revD_MC\LMK_CDM_MODE\16CH_MODE


    Sincerely,
    Olu

  • In reply to Olu Sodipe:

    Hi Olu-san,

    Our customer is using not TSW14J56revD but other FPGA board.
    When the customer's FPGA board is used, it can be operated even with the specification I wrote the other day.

    So, please teach me the register settings of LMK04826 first.
    The customer must operate the board with this specification.

    ----------------------------------------------------------------------------------------------
    Mode 1
      Input:
          CLKin 1 = 40 MHz (using an oscillator on the board)
      Output: 
          DCLKOUT 0 (FPGA_CLK) = 72 MHz
          DCLKOUT 2 (ADC_CLK) = 72 MHz
          SDCLKOUT 1 (FPGA_SYSREF) = 7.2 MHz
          SDCLKOUT 3 (ADC_SYSREF) = 7.2 MHz
    ----------------------------------------------------------------------------------------------
    Mode 2
      Input:
          CLKin 1 = 40 MHz (using an oscillator on the board)
      Output:
          DCLKOUT 0 (FPGA_CLK) = 102 MHz
          DCLKOUT 2 (ADC_CLK) = 102 MHz
          SDCLKOUT 1 (FPGA_SYSREF) = 10.2 MHz
          SDCLKOUT 3 (ADC_SYSREF) = 10.2 MHz

    ----------------------------------------------------------------------------------------------

    Would you please send us the config file of that GUI software?

    Best regards,
    M. Tachibana

  • In reply to Masanori Tachibana:

    Hi Olu-san,

    The customer has been trying to output the following signals many times, but he has not been able to set it yet.
    Customers are also in trouble now.
    Please teach me the register setting of LMK04826 for the signal.

    ----------------------------------------------------------------------------------------------
    Mode 1
      Input:
          CLKin 1 = 40 MHz (using an oscillator on the board)
      Output: 
          DCLKOUT 0 (FPGA_CLK) = 72 MHz
          DCLKOUT 2 (ADC_CLK) = 72 MHz
          SDCLKOUT 1 (FPGA_SYSREF) = 7.2 MHz
          SDCLKOUT 3 (ADC_SYSREF) = 7.2 MHz
    ----------------------------------------------------------------------------------------------
    Mode 2
      Input:
          CLKin 1 = 40 MHz (using an oscillator on the board)
      Output:
          DCLKOUT 0 (FPGA_CLK) = 102 MHz
          DCLKOUT 2 (ADC_CLK) = 102 MHz
          SDCLKOUT 1 (FPGA_SYSREF) = 10.2 MHz
          SDCLKOUT 3 (ADC_SYSREF) = 10.2 MHz

    ----------------------------------------------------------------------------------------------

    Best regards,
    M. Tachibana

  • In reply to Masanori Tachibana:

    Hi Masanori-san,

    The ADS52J90 settings for both customer's configurations can be found in the folder I mentioned above even if the customer is not using the TSW14J56revD board. By installing the right version of HMC-DAQ GUI software, the configuration files should be added to the folder.

    The figure below represents the clocking setup on the ADS52J90 board

    Once the PLLs are locked to a target frequency, the VCO is just then divided down to the needed clock frequencies. After starting the ADS52J90EVM, run the 12b 12x JESD script from the folder I mentioned above then modify the following registers as follows;

    0x100 0x1B
    0x102 0x00
    0x103 0x00
    0x108 0x1B
    0x10E 0xF0
    0x116 0xF0
    0x138 0x00
    0x13A 0x01
    0x13B 0x0E
    0x13E 0x02
    0x147 0x18
    0x156 0x04
    0x15A 0x0A
    0x161 0x19
    0x162 0x5C
    0x168 0xF3

    That should get your PLLs locked with a VCO frequency of 1944MHz which is then divided down to 72MHz (divided by 27 using registers 0x100, 0x108) for FPGA_CLK and ADC_CLK respectively.

    The SYSREF signals are divided off of the same VCO frequency of 1944MHz(by 270 to 7.2MHz) using registers 0x13A, 0x13B.

    Therefore, for case 2, all your customer has to do is leave everything else the same but change the divider settings for the respective clocks.

    Sincerely,

    Olu