The signal chain would be TX517 -> transducer -> AFE58XX -> TSW1400.
The LNA’s DC offset correction circuit consists of a HPF with a corner frequency set by CBYPASS that has to be changed to 1uF in order to prevent attenuation of the input signal for signals <100kHz.
Gemetal Medical Transducer from Sound Technology for US.
Vermon Transducer Company for Europe.
The FPGA firmware source code for the TSW1400EVM can be accessed from the TSW1400EVM product folder at www.ti.com.
Here are some resources to assist with deserializing serial LVDS data on the receiver side.
The following TI adapters can be used with our serial LVDS AFExx and ADSxxxx devices to interface with Altera and Xilinx FPGA boards.
For Coefficient memory accesses, the SPI write is different than a standard SPI write of 24 bits. It will be a single SPI cycle access of 120 bits (8 bits of address followed by 112 bits of data with MSB first) The SEN signal should be low for the entire write time.
User-defined device settings cannot be used to configure the AFE5809 at startup but specific configuration steps can be saved in a CMD file by using the GUI’s “record command” and “save command” features.
SYNC and SYSREF pins’ termination were recently updated to the architecture below in order reduce glitches and false triggers.
Unused JESD CML pins, CLK_1X, CLK_16X, NC pins can be left floating.
The AFE5801 EVM ships with the adapter card for the TSW1400EVM. It does not need to be ordered separately.
The TX517 EVM requires all 11 power supplies and their functions are listed in the datasheet pin description section.
Digital control of TGC via SPI intended for fixed attenuation/testing. Analog control TGC is piecewise linear but it is possible to specify the timing of uniform and non-uniform time gain control using programmed settings on our AFE5801, AFE5851, AFE5816, AFE58JD16 devices.
The LVDS bit clock and the frame clock scales down based on the decimation factor.
The LVDS bit clock frequency (LCLK) is dependent on the sample rate and the type of wire interface (1-wire or 2-wire). And the sample rate is factor of the input clock rate and the decimation factor.
The TSW14xx temporary time domain data can be accessed in this location: C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\ADC temp.bin
1ps typical jitter for clock source acceptable for the device.
Test pattern “none” means Analog signal input as opposed to ramp, sine, etc patterns.
Ideally, these supplies are kept separate to reduce risk of cross coupling from digital to analog domain. However, it can be done if care is taken in providing good power supply filtering close to each power DUT pin before combining to the central supply
We can’t externally bias our ADC inputs as they are already internally biased to a specific voltage.
Typical aperture delay is specified in the corresponding device datasheet. It has both digital (clock skew between channels, device variation from lot-to-lot) and analog contributing factors (internal HP, LP filter variations in propagation delay).
The ADS5294 is an 8 analog channel device therefore there are only 8 SMA's for the analog inputs. It is the digital output that can be used in 1-wire or 2-wire mode. In 1-wire mode there are 8 LVDS differential pairs corresponding to the 8 analog inputs. In 2-wire mode, there are 16 LVDS differential pairs with each analog input getting 2 outputs.
The output of the AFE5801 is serial LVDS at 0.5Gbps or more. You would have to find a PC interface that can capture data that quickly.
The TX810 is the only solution that our Medical Ultrasound team has for this type of application. It is our only T/R Switch.
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