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ADS52J90: About behavior when data rate in JESD204B is more than 5Gbps

Part Number: ADS52J90

Hello support team,

Our customer is now evaluating the high speed communication of JESD204B using ADS52J90.
I have some questions about the behavior when the following conditions are set.
  Data rate of JESD204B = 6.12 Gbps
  Frequency of device clock = 102 MHz
  L = 4, M = 16, F = 6, K = 4, N = 10, N '= 12, TailBits = 2 bits
  Built-in test pattern is used. (No analog input signal is used.)

1. Does ADS52J90 function well when the settings above are set?
(Though it is described as "5-Gbps JESD Interface" in the data sheet.)

2. If ADS52J90 does not function, which part does not work?
(Where is the bottleneck part of ADS52J90?)

Best regards,
M. Tachibana

  • Hi Masanori-san,

    The ADS52J90 will work just fine for a 6.12Gbps data rate but your trace length might have to be shorter. Figure 40 shows the device's jitter performance for different trace lengths up to 6.4Gbps.
    The "5Gbps JESD interface" note is because of the JESD204B standard's max jitter requirements.

    Sincerely,
    Olu
  • Hello Olu-san,

    Thanks for your advice.
    Our customer understood that JESD204B of ADS52J90 can operate even at 6.12 Gbps.

    Then I have three more questions.

    1) The customer understood that total jitter depends on the data rate and trace length, and that the data rate of 5 Gbps is a limitation from the maximum jitter standard of JESD204B.
    Is these understanding correct?

    2) The customer presume that specification of this maximum jitter means TJ = 0.30 p-pUI in "Transmitter Electrical Specifications (LV-OIF-6G-SR)" of the JESD204B standard.
    Is this correct?

    3) The customer presume that it is necessary to make trace length 50.8 mm (2 inches) or less in order to satisfy the maximum jitter standard under the condition of 5 Gbps / PRE_EMP = 15 using ADC52J90.
    Is this understanding correct?

    Please teach me.

    Best regards,
    M. Tachibana

  • Hi Masanori-san,

    As an example, I took some data in the lab today using the ADS52J90EVM and the TSW14J56revD;

    5.1MHz input signal, 8 ADC channels/lane (16 channel, 12x, 12b mode). For an ADC sampling frequency of 20MHz, JESD204B lane rate at 3.2Gbps.

    Then, with all other conditions unchanged, ADC sampling frequency was increased to 31.25MHz (lane rate now 5Gbps) which led to ~0.6dB drop in SNR.

    Keeping everything else constant again, the ADC sampling frequency was increased to 40MHz (lane rate now 6.4Gbps) and this resulted in another ~0.5dB drop in SNR.

    So yes, your understanding is correct but the JESD204B standard total jitter specifications has some margin regarding how it affects system performance.

    Sincerely,

    Olu

  • Hi Olu-san,

    Thanks for your information.

    By the way, combining ADS52J90EVM and TSW14J56revD, how long is the total length of pattern which is signal path of JESD204 on the board?
    Could you advise me?
    The customer is concerned about the total length of JESD204 signal path on the boards since he would like to operate at high speed (6.12 Gbps).

    Best regards,
    M. Tachibana
  • Hi Masanori-san,

    For the combination of the ADS52J90EVM and the TSW14J56revD we have in the lab, the trace length from the ADS52J90 to the FPGA on the TSW14J56revD is >6inches.

    Sincerely,
    Olu
  • Hello Olu-san,

    Thanks for your information.
    I have already informed our customer.
    And the customer understood.

    Best regards,
    M. Tachibana