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ADS52J90EVM: TWS14J56 capture with ADS52J90 XTAL40MHz clock source

Part Number: ADS52J90EVM
Other Parts Discussed in Thread: LMK04826, ADS52J90

Hi,

I have problems capturing data (ramp signal) from ADS52J90EVM via TWS14J56EVM. I set up jumpers on ADS... to use on-board 40MHz XTAL as a clock source for LMK04826. Two or three capture requests on HSDC Pro are successful, but the next shows regularly degraded signal:

The next attempt to capture inevitably ends up with timeout error:

Power cycling the TSW board allows for another 2 to 4 capture requests and the situation repeats. The degraded ramp signal looks pretty much the same on each channel.

On TSW board, led D4 blinks ca 0.5Hz, D2, D3, D5, D6, D7 are off,  D1, D8 are ON. All the blue power monitoring leds are on.

On ADS board, no led (except for D8 power indicator) is on (I expected D3/D4 PLL lock leds to be on...).

Jumper settings on ADS board are:

JP40: 2-3 (LMK ADC_CLK)

JP41: 1-2 (LMK SYSREF) 

JP7: 2-3 (XTAL detrmined by JP8 to LMK CLKIN)

JP8: 2-3 (40MHz XTAL)

JP6: 1-2 (XTAL Powered with 3.3V)

JP4: shorted (XTAL 100MHz powered) - I have test run with JP4 open as well.

As for HMC GUI - I use default configuration loaded on startup with JESD: 16ch, 16x 14b 4ADC/Lane mode (GUI version is 2.8)

The configuration loaded by HSDC Pro (version 4.50, no patch applied)  looks matching the HMC configuration:

As a ADC sampling frequency I set 40M in HSDC GUI.

Both boards are powered from single power source - a PC power supply (25A on +5VDC rail).

I will be grateful for any help resolving the problem.

  • Hi Piotr,

    What is the current limit set on the single power supply +5V rail?
    Also can you clarify what you meant by '(25A on +5VDC rail)'? Are you measuring 25A on the 5V supply?
    Can you try separating out the power supplies for the TSW1400 and the ADS52J90 EVM?
  • Hi Praveen,
    Thank you for prompt response.
    I meant, the power supply's maximum current is 25 amps. The actual combined (ADS + TSW board) current draw is max. 2.5A during HMC GUI initialization phase (after loading FPGA firmware) and typically 2.1A during capture. During early experiments, I had powered the boards with separate power supplies, but those PS's had smaller maximum current rating (one 2.5A and the other - 1.5A), so I switched to a power supply with larger current margin. Anyway, the behaviour with separate power supplies was the same.

    What I don't understand is, that GTX_CLCK on TP4/TP5 of ADS board has 40MHz waveform (watched on oscilloscope). My understanding is, that when I put a 40MHz sampling frequency in the HSDC GUI (I get the message, that "JESD reference clock between device EVM and TSW14J56revD needs to be set at 160M), there goes background interprocess communication between HSDC GUI and HMC GUI and HMC is informed on the new Fs set (in fact, the value in HMC input line is updated) and than, the HMC reprograms the ADS board LMK device, to generate on DCLKOUT0 output a 160MHz clock. This clock should be observable on TP4/TP5. But, as I said, there is 40MHz waveform there and no LED D3/D4 indication on LMK PLL Lock.

    Do I get it right? Is this the cause of the problem?
  • Hi Piotr,

    You are right that the clock is the likely cause of the problem.  You need a 160MHz GTX clock to the TSW14J56 for a 40MHz Fs with 4L JESD but the LMK on the ADS52J90EVM is only setup in divider mode (PLLs not active).

    The EVM user guide recommends an external input clock at the GTX clock frequency for this reason. If you want to use the onboard 40MHz crystal as an input to the LMK, you will have to configure the LMK's PLLs to generate the higher GTX frequency of 160MHz. This post should get you started with D3/D4 coming on to signify PLL lock.

    Sincerely,

    Olu

  • Hi Olu,

    Thank you very much for your response and for the reference post on PLL configuration. Following instructions from this post I've got both PLL stages locked. I think, I know by now how to configure LMK04826 to get desired clocks, but it looks, there are some aspects of the ADS52J90EVM / TSW14J56EVM communication, that I don't get. These are most probably layman's problems, so I'll be more than grateful if you help me sort it out.

    First of all, i guess, that even with the  LMK04826 in divider mode, with CLK1IN sourced from 40MHz Xtal,  the capture process should be successful, if I demand ADC output rate such, that the corresponding JESD reference clock  is 40MHz, right? I have tried that. My setup was default initialization of HMC GUI with  16ch 16x 14b 4ADC/Lane, ramp pattern and the HSDC Pro with 10M ADC Output Data Rate.  The HSDC Pro message was that lane rate was 800M and the required JESD reference clock was 40M.  I have checked TP8/10 (ADS CLKP/M) and there was 10M clock there. And the TP4/TP5 (FPGA GTXCLK) showed 40M clock. The calculation, as I understand it, was correct: 8 octets per frame times 10bits (after 8b/10b encoding) times 10M ADC output rate gives 800M. Divided by 20x data rate gives 40M.

    Unfortunately, the capture process went exactly, as initially described: one or two successful attempts of getting 65536 samples, next attempt with distorted ramp and yet another finished with "Read DDR to file TIMED_OUT_ERROR". TSW14J56 power cycle reset was required to regain functionality (CPU RESET was not enough).  What do I wrong?

    Maybe there is something wrong with the synchronization? The Instrument Options->Dynamic configuration dialog read JESD IP Core_Subclass = 1.

    But the configuration loaded by default by HMC GUI, as seen on the  ADC->JESD 0 tab shows subclass 0 config:

    There is a 1.666MHz (40M/24) clock on the TP6/TP7 (FPGASYSREFP/M). But there is no SYSREF on TP9/TP11 (ADC_SYSREF). No wonder, as LMK04826 has SDCLKOut3 in powerdown. I have played with setting subclass 1 for ADC and clearing the SDCLKOut3 powerdown. but all those failed in more or less spectacular way. 

    I'm also not sure, why the ADS52J90EVM User Guide in par. 3.3 (EVM Clock Configuration) reads that Serdes lane rate is 10 times reference clock for target lane rate below 1G and 40 times reference clock for target > 1G. Either your post and HSDC Pro Messages suggest 20x multiplier regardless of the target lane rate?

    Peter

  • Hi Peter,

    If you look at register 115 and page 52 of the datasheet, you can verify what subclass of JESD204B you are currently running on your device. The hidden debug options in HMC-DAQ GUI have not been tested/verified and are not recommended for customer use.

    Regarding the lane rate being 10X reference clock, some earlier scripts/configuration files were setup for different 10X, 40X, 20X options but unless stated otherwise, assume 20X for now.
    As there is only one ADS52J90 under test, the ADC_SYSREF pin is not active by default for the ADS52J90EVM even in JESD204B subclass 1 mode.

    Looking at the issues you are having so far, I'ld recommend first starting with something simple to verify board functionality. Setup the ADS52J90EVM in external clock mode where the FPGA reference clock is input on J75 (10dBm+) and the LMK is in its default bypass/divider mode according to the user guide (use the default 16ch 16x 14b 4L config under output format).

    Then, try a ramp and analog signal capture while verifying that D4 is blinking on the TSW14J56revD board (signifying the board is getting a reference clock). Verify that the ADS52J90EVM is providing the required clocks on TP9, JP40 and TP4.

    Update your results and we'll go from there. Thanks.

    Sincerely,
    Olu

  • Hello, Olu,

    Thank you for your help. I have finally spotted down the source of problems. It is USB connection between TSW14J56 and PC. When I plugged the TSW14J56 into another USB port, the problem disappeared. It is Renesas USB3 Controller integrated on my Asus mobo and I have switched to another port on the same physical hub (as reported by USBView). The basic communication with TSW14J56 works well on both ports, but the first one has apparent problems with super(?)speed data transfer. I don't know, maybe some hardware mulfunction, maybe some driver side effect. If you would like to investigate problem closer, I'm at your service.
    BTW, I have played much with this debug interface for configuring LMK08426 and it's very handy and seems to work well.
    OK, I have a working set, it's time for me to dive seriously into JESD204B standard :-).

    Thank you again.

    Best regards,
    Peter