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ADS52J90EVM: Unable to modify Register 0x50 INC_JESD_VDD value

Li Zhang71
Prodigy 90 points
Part Number: ADS52J90EVM
Other Parts Discussed in Thread: ADS52J90

Hello there,

Our design have ads52j90 interfaces with xilinx kcu105. We were able to transfer data correctly with JESD interface.  However, the JESD interface frequently lose sync.  

Our configuration is 16 channel, 8 lanes, 100Msps and 10bit adc resolution (corresponding to lane rate of 4Ghz).  

The ads52j90 user guide stated that "At higher speeds (beyond 4 Gbps), the LDO voltage drops because of increased switching currents. To improve the jitter at higher speeds, restore the LDO voltage with the INC_JESD_VDD register control."

We can't modify register 0x50 INC_JESD_VDD value through GUI.  We also tried script but got an error message.  Please advice how to change register 0x50 or anything we can do to improve JESD interface stability at 4Ghz lane rate or greater.

Attached the error message.

Best Regards,

Li

  • 0
    TI__Expert 4145 points

    Hi Li,

    What exactly do you mean by the JESD interface frequently loses sync?

    Register 0x50 is actually not mapped in the GUI as you observed. I'll have to talk to my software team to try to find any workarounds to programming that register using the GUI.

    In the meantime, you can also try using a cheap microcontroller to program that register on the device via SPI. The test points shown below can be used to directly program the device.

    Sincerely,

    Olu

  • 0 in reply to Olu Sodipe
    TI__Expert 4145 points

    Hi Li,

    There is also a direct memory write function within the GUI that you can play with. It should not require the register to be mapped for a SPI write.

    Sincerely,

    Olu