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AFE5809: AFE5809 interfacing with DSP

Mariusz Hajduk54
Prodigy 70 points
Part Number: AFE5809
Other Parts Discussed in Thread: 66AK2H12

Hi,

 I've got some doubts how to interface ultrasound AFE's like AFE5809 with DSP (C6678) as suggested in www.ti.com/.../afe5809.pdf. Suppose I want to design 32-channel ultrasound scanner. Once I have every scan line data from all the channels in memory, the software based beamforming and post processing seams to be a great idea.

However, capturing this data directly from AFE by DSP is still misterious for me. First of all, suggested DSP doesn't have a built-in deserialization mechanism, and also synchronization with bit_clk and frame_clk with dsp_clk seams not to be possible.

Suppose, I will use FPGA as an interface between AFE's and DSP. Deserialization in FPGA is not a problem, but writing captured data from all the channels simultanuesly to external memory will require 32x12bit=384bit wide word or in the other words 32 16-bit wide memory chips. In such a case, I will quickly run out of available FPGA I/Os, not to mention about the number of DDR interfaces possible to be implemented in FPGA.

A single scan line will require 10390x12bitsx32channels=4Mbits (scannig depth=20cm, sampling=40MHz), therefore storing the data in FPGA on-chip BRAM and then transferring them to DSP as the scanning is completed, is also  not possible unless I will use a very expensive FPGA devices. FPGA devices available at reasonable prices have about 2Mbits on-chip BRAM.  

I would appreciate for any suggestions. Some reference designs are very welcome too.

Best Regards,
Mariusz

  • 0
    Prodigy 70 points
    Correction:
    Link in the above threade should be to www.ti.com/.../sprabo0.pdf
  • 0 in reply to Mariusz Hajduk54
    TI__Mastermind 49176 points
    Hi Mariusz,

    Thank you for the inquiry about the application usage of the device AFE5809 with DSP.
    I will check with the team and will get back to you by tomorrow.
  • 0 in reply to Praveen Aroul
    Prodigy 70 points

    Hi Praveen,

    One week has passed and still no answer.

    Regards, Mariusz

  • 0 in reply to Mariusz Hajduk54
    TI__Mastermind 49176 points
    Hi Marisuz,

    I apologize for the delay in my response.

    I was checking with my team regarding the paper.
    It seem like the authors of the paper are no longer associated with UW.

    As you pointed out, typically FPGAs are used as an interface between the AFE and the DSP with some kind of LVDS to serdes implementation compatible with the DSP interface.

    I am looping in the DSP team to help with the questions related to the compatible interface and the memory limitations on the DSP.
  • 0 in reply to Praveen Aroul
    Prodigy 70 points
    Hi Praveen,
    I think it's a good idea to ask DSP team about it, because such a problem is in my opinion related not only with ultrasound AFE's but with a wide range of multichannel high speed ADC's. In my design LVDS iserdes2 (Spartan6) and signal processing works fine, however some important functions like doppler processing are difficult to implement because of limited FPGA resources. DSP when interfaced, could be a nice and flexible solution. I'm looking forward to hear from you soon.
    Regards,
    Mariusz
  • 0 in reply to Mariusz Hajduk54
    TI__Mastermind 46460 points

    Mariusz,

    What is your sustained throughput requirement or is this simply 'capture-transfer-process'?  If it is 'capture-transfer-process', you could implement an external SRAM on the FPGA for temporary storage and then use the EMIF16 to transfer the data into the DSP for processing.  Note that this will be relatively slow.  An alternative that can support the full bandwidth, real-time streaming of the AFE5809 would be to use an FPGA with an LVDS port to the AFE and then a PCIe link into the C6678 and into the attached DDR3 memory.  This could be used to stream the sensor data into the C6678 in real-time as it is being captured.  This would enable continuous beam-forming computations to occur without delays for transfer and processing.  FPGAs with PCIe ports are readily available and affordable.  This is also scalable in case your processing needs exceed the capability of a single C6678.

    You can prototype this using EVMs.  An EVM for the AFE5809 can be connected to an FPGA EVM that is then connected to a C6678 EVM.

    Also note that we have a newer product with higher integration that may be of interest.  Our 66AK2H12 device also contains 8 C66 DSP cores but it is mated with a Quad-core ARM processor that can run an OS like Linux and manage all of the other housekeeping functions like driving a display and any other human-machine interface functions required.

    If you do not require 8 DSP cores for your computations, the C6657 is a 2-core equivalent to the C6678.  Similarly, if you can use 2 DSP cores and want ARM integration, our family of AM572x devices combine 2 ARM cores and 2 DSP cores in a highly integrated product with built-in display capability.  All of these devices support PCIe communication links.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 70 points
    Hi Tom,

    Thank you very much for your response. However, the problem is both 'capture-transfer-process' and data throughput. Let's consider 'capture-transfer-process' first. In general, your suggestion for buffering the captured data from FPGA on external SRAM is OK, but take a closer look on a problem. For a typical ultrasound scanner I need at least 32 channels for an acceptable beamforming quality. Data from each channel is 12 bit. This produces a 384 bit wide data captured simultanously. Attaching the external SRAM to FPGA will result of run-out of available IOs of the FPGA (unless I will use top expensive devices). Such a solution produces also one scan line processing latency, but it is acceptable.

    An alternative PCIe streaming solution is to be considered. In fact I have no experience with PCIe and I have to read some papers first. What is your opinion about transfering 384-bit wide data with the rate 40MHz (15.36Gbps)? Is it possible? If yes, I would like to ask you for recommendation of FPGA EVM's (Xilinx only) and DSP EVM's to make some experiments with it.

    Or maybe you have some other ideas?

    Best Regards,

    Mariusz
  • 0 in reply to Mariusz Hajduk54
    TI__Mastermind 46460 points

    Mariusz,

    How did you get to 15Gbps?  The datasheet for the AFE5809 states that the LVDS interface transfers data at 910Mbps.  14-bit samples at 65 MSPS yields a raw throughput of 910Mbps.  A single lane PCIe at GEN1 operates at 2.5Gbps and should be able to easily transport over 2Gbps after allowing for overhead.  The C6678 has 2 lanes that can operate at GEN2 (5Gbps) so that the total PCIe bandwidth available is 10Gbps.

    Even with the 'capture-transfer-process' implementation, you do not need to store the data at 384 bits wide.  You can easily pack this into a 32-bit ASRAM at a 33MHz.  This can be implemented on relatively inexpensive FPGAs.

    Am I missing something?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 70 points

    Hi Tom,

    You have missed something very important. AFE5809 is the 8-channel ultrasound AFE and 910Mbps is a single channel data rate transfer @65MHz sampling rate for 14-bit wide word. I have made much easier assumption, it meens ADC is clocked @40MHz with 12-bit word. In my present 32-channel design I use 4 AFE5809 chips, therefore it is 32channels x 12bit x 40MHz sampling=15.36Gbps. In fact before deserlialization every single LVDS lane is in my case 12bit x 40MHz=480Mbps, but when transfering all the data from FPGA to DSP we have to consider all 32 channels. In my design all 32-channel deserialization, Transmit beamforming, Receive beamforming, demodulation and many other associated functions are fitting in XC6SLX45 FPGA. However, logical resources of this device are limited and I think some processing functions, especialy receive beamforming could be implemented in DSP with more sofisticated and accurate algorithms on raw RF data.

    The sprabo0 gives me a hope that it is possible, but the hardware interface between AFE and DSP is still a mistery for me.

    And finaly, you wrote "Even with the 'capture-transfer-process' implementation, you do not need to store the data at 384 bits wide.  You can easily pack this into a 32-bit ASRAM at a 33MHz."

    Now, I am missing something. Can you explain the above?

    Regards,

    Mariusz

  • 0 in reply to Mariusz Hajduk54
    TI__Mastermind 46460 points

    Mariusz,

    Forget the 'capture-transfer-process' question.  The challenge here is the need for 8 channels simultaneously per AFE and 4 AFE devices for an implementation needing 32 LVDS streams at a rate of up to 910 MHz for each.  That is an incredible amount of raw data for processing.  Have you done any benchmarking to determine how many DSP cores are needed to perform the required processing in the allowed amount of time?

    You state that you are currently bringing that much streaming data into an  XC6SLX45 FPGA and performing the beamforming in the hardware multipliers.  What additional processing are you needing that cannot be done in the FPGA?  You might want to use the FPGA for data aggregation and pre-processing and then use the DSPs for final processing and analysis.  This would reduce your bandwidth into the DSPs to a manageable amount.  PCIe is still a good choice.  The XC6 family of FPGAs have PCIe as an option with a T suffix.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Mariusz,

    Do you need any further assistance?  If we do not see a response in the next week, we will close this thread.

    Tom