DRV8834 – About VREFO output timing

Hide

Guru 21045 points

Other Parts Discussed in Thread: DRV8834

Hi Team,

Our customer are evaluating DRV8834.

Could you please let me ask the following question?

[Question]

After the Sleep mode was released (nSLEEP pin = Low -> High), when does the output voltage of VREFO appear?

Could you please let me know it if you have this value(min / typ / max)?

According to our customer, their evaluation result is “150usec”.

(Please refer to attached Figure.)

over 9 years ago

0 Rick Duncan over 9 years ago

TI__Guru** 114905 points

Hi Kanemaru-san,

We are currently investigating and plan to provide an answer within a day.

0 Hide over 9 years ago in reply to Rick Duncan

Guru 21045 points

Hi Rick-san,

Thank you for your prompt reply and your kind support!

I’m looking forward to hearing from you.

Regards,

Kanemaru

0 Soichi Nishimura over 9 years ago in reply to Hide

TI__Expert 4455 points

Kanemaru-san,

VREFO is created from the VINT regulator. Therefore any variations of VINT capacitor and VINT external load current affect the time to VREFO. If we assume the load and capacitor remain the same as the experiment for which customer got 150us delay, we can tell him min time would be ~ 50us and max would be ~350us. The time between nSLEEP and VREFO will increase when he uses bigger capacitance or higher current load.

Best Regards,

Soichi Nishimura

0 Hide over 9 years ago in reply to Soichi Nishimura

Guru 21045 points

Hi Nishimura-san,

I greatly appreciate your cooperation!

I will report this result to our customer.

Regards,

Kanemaru

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DRV8834 – About VREFO output timing